U. Glaeser

FIGURE 10.37 Time borrowing for single-phase, latch-based design.
also design complexity and verification effort. Because of these reasons, single latch-based designs are
rarely used in practice.
Notice that the latch setup time is not part of Eq. (10.5). Consequently, it can be concluded that the
setup time does not affect the timing of a latch-based design (although the latency of the latch does).
This is true except when time borrowing is applied. This is the subject of the next subsection.
Time Borrowing
Time borrowing is the most important aspect of a latch-based design. So far it has been said that in a
latch-based design critical signals should not be blocked, and that the max-timing constraint is given by
Eq. (10.2); however, depending on the latch placement, the nonblocking requirement can still be satisfied
even if Eq. (10.2) is not. Figure 10.37 illustrates such a case. With reference to the model in Fig. 10.33,
input D1 is assumed to be blocked. So the transition of Q1 happens a CK-to-Q delay after clock (TCKQ) and starts propagating through the max path. As long as D′ 1 arrives to the receiving latch before the setup
time, the D-to-Q transition is guaranteed to be nonblocking. In this way, the propagation of D′ 1 is allowed
to “borrow” time into the next clock cycle without causing a timing failure.
The maximum time that can be borrowed is determined by the setup time of the receiving latch. The
timing requirement for such condition is formulated as follows:
and rearranged as:
© 2002 by CRC Press LLC
CK
D1 Q1 D 1 ′
Q 1 ′
Transparent
T CKQ
T CYC
(10.6)
(10.7)
By subtracting Eq. (10.2) from Eq. (10.7), the maximum amount of time borrowing, T borrow, can be
derived and it is given by
Assuming that T CKQ ≈ T DQ, Eq. (10.8) reduces to
Opaque
Transparent
TSETUP (10.8)
(10.9)
So the maximum time that can be borrowed from the next clock cycle is approximately equal to the
length of the transparent period minus the latch setup time.
Because time borrowing allows signal propagation across a clock cycle boundary, timing constraints
are no longer limited to a single pipeline stage. Using the timing diagram of Fig. 10.37 as a reference,
T MAX
TCKQ + Tmax < TCYC + TON – Tsetup T ON
Tmax < TCYC + TON – ( Tsetup + TCKQ) Tborrow = TON – ( Tsetup + TCKQ) + TDQ Tborrow =
TON – Tsetup T DQ