U. Glaeser

FIGURE 21.14 (a) Clock-powered static logic arranged in pipeline stages with DD/DS P2LC and (b) net computation
time within a cycle.
FIGURE 21.15 Clock-powered static logic arranged on pipeline stages with SD P2LC (a) for cycle- and (b) for
phase-granularity computations.
of stretching the fall time is that the input cutoff voltage for the E-R latch will occur earlier in the clock
phase. The net result is that for a fixed cycle time, the amount of computation that can be done during
a cycle is decreased to reduce energy dissipation. For phase-granularity computations (i.e., mostly precharged
and pass-transistor logic—Fig. 21.13(b)), the slow clock phase edges reduce the computation
time four times within a cycle as opposed to twice per cycle for cycle-granularity computations (i.e., static
logic—Fig. 21.14(b)). The benefit of phase-granularity computations is that more opportunities for
energy recovery are available, since nodes can be clock-pulsed on both phases. This also results in balanced
capacitance for both clock phases, which may be required for high-efficiency clock drivers; however,
phase capacitance can be balanced for cycle-granularity computations if a phase-granularity computation
is introduced in a sequence of pipeline stages. For example, assume a system with N pipeline stages. Also
assume that a phase-granularity computation is introduced after the N/2 pipeline stage while the rest of
the stages are cycle-granularity computations. Then the clock-powered nodes of the first N/2 stages would
be driven by one phase, whereas the clock-powered nodes of the final N/2 stages would be driven by the
other phase.
© 2002 by CRC Press LLC
ϕ 2
ϕ 2
ϕ 2
Latch
V th
ϕ 1
ϕ 1
ϕ 2
ϕ 1
∧ϕ1 CB DD/DS Static Latch CB
P2LC Logic
ϕ 1
1 cycle
(a)
(b)
ϕ 1
t ccs
∧ϕ1 Latch CB SD Latch Static Latch CB
P2LC
Logic
ϕ 1
evaluates on ϕ 1
ϕ 1
1 cycle
(a)
ϕ 2
Latch CB SD Static Latch CB
P2LC Logic
1 cycle
(b)
ϕ 2
SD
P2LC
ϕ 2
Static
Logic
evaluates on ϕ 2
ϕ 1
ϕ 2
Latch
ϕ 1
CB