U. Glaeser

In some literature, the authors like to group P leakage and P static together and call it as the static component
of power.
The switching component of the power occurs when energy is drawn from the power supply to charge
parasitic capacitors made up of gate, diffusion, and interconnect capacitance. For properly designed
circuits, the switching component will contribute more than 90% of the power consumption, making
it the primary target for power reduction [12]. A system level approach, which involves optimizing
algorithms, architectures, logic design, circuit design, and physical design, can be used to minimize
power. The physical capacitance can be minimized through choice of substrate, layout optimization,
device sizing, and choice of logic styles. The choice of supply voltage has the greatest impact on the
power-delay product, which is the amount of energy required to perform a given function. From the
expression for the switching component of power (P switching = C LV 2 f ), it is clear that if the supply voltage
is reduced, the power delay-product will improve quadratically. Unfortunately, a reduction in supply
voltage is associated with a reduction in circuit speed. However, if the goal is to increase the MIPS/Watt
in general purpose computing for a fixed level, then various architectural schemes can be used for
voltage reduction.
The short-circuit power dissipation, P short-circuit, is due to short-circuit current, I sc. Finite rise and fall
time of the input waveforms result in a direct current path between supply voltage V DD and ground, which
exists for a short period of time during switching. Such a path never exists in dynamic circuits, as precharge
and evaluate transistors should never be ON simultaneously, as this would lead to incorrect evaluation.
Short-circuit currents are, therefore, a problem encountered only in static designs. Through proper choices
of transistor sizes, the short-circuit component of power dissipation can be kept to less than 10%.
Leakage power, P leakage, is due to the leakage current, I leakage. Two types of leakage currents seen through
in CMOS VLSI circuits: reverse biased diode leakage current at the transistor drain, and the subthreshold
leakage current through the channel of an “OFF” device. The magnitude of these leakage currents is set
predominantly by the processing technology. The sub-threshold leakage occurs due to carrier diffusion
between the source and the drain when the gate-source voltage, V gs, has exceeded the weak inversion
point, but still below the threshold voltage V t. In this regime, the MOSFET behaves almost like a bipolar
transistor, and the subthreshold current is exponentially dependent on V gs. At present P leakage is a small
percentage of total power dissipation, but as the transistor size becomes smaller and smaller and the
number of transistors that can be integrated into a single silicon die increases, this component of power
dissipation is expected to become more significant.
Static power, P static, is due to constant static current, I static, from V DD to ground when the circuit is not
switching. As we have seen earlier, complementary CMOS combines pull-up and pull-down networks
and only one of them is ON at any given time. Therefore, in true complementary CMOS design, there
is no static power dissipation. There are times when deviations from the CMOS design style are necessary.
For example in special circuits such as ROMs or register files, it may be useful to use pseudo NMOS
logic circuit due to its area efficiency. In such a circuit under certain output conditions there is a constant
static current flow, I static, from V DD to ground, which dissipates power.
The power reduction techniques at the circuit level are quite limited when compared with the other
techniques at higher abstraction levels. At the circuit level, percentage power reduction in the teens is
considered good [11]; however, low-power circuit techniques can have major impact because some
circuits are repeated several times to complete the design. For example, adders are one of the most
often used arithmetic circuits in digital systems. Adders are used to perform subtraction, multiplication,
and division operations. Reducing power consumption in adders will result in reduced power consumption
of many digital systems. Various different types of adders have different speeds, areas, power
dissipations, and configurations available for the VLSI circuit designer. Adders or subsystems consisting
of adder circuits are often in the critical path of microcomputers and digital signal processing circuit;
thus a lot of effort has been spent on optimizing them. As shown in Fig. 2.10, the straight forward
realization of a CMOS full adder will require 28 transistors. This adder is not optimized for power
dissipation. Recently, there has been tremendous research effort in the design and characterization of
low-power adders. The 14-transistor (14T) full adder proposed by Abu Shama et al. [13], dual value
© 2002 by CRC Press LLC