U. Glaeser

eal-time. Although floating-point processors give very effective calculation performance, the fixed-point
processors are also often used, because they are characterized by a much lower supply energy consumption
(e.g., 0.05 mW/MIPS for the TMS320C55x processors) and are, moreover, much cheaper [50].
In order to facilitate communication with the host processor (computer), modern DSPs are equipped
with a special interface—the host port interface (HPI) [49]. Using the HPI, the host processor has an
access to the memory of the digital signal processor. Physical connection of processors uses 8- or 16-bit
parallel data bus and several control lines. The HPI performs also a boot operation of the DSP. Due to
this possibility an additional boot memory is not necessary. Selected DSPs provide also a glueless interface
to the peripheral component interconnect (PCI) bus.
The next interesting feature of modern DSPs is the use of a buffered serial port (BSP) [49]. BSP makes
a high-speed communication with external devices, e.g., ADCs and DACs, possible. In relation to a typical
serial port, BSP offers enhanced features, which allow for a direct read/write operations from/to the
memory connected to the signal processor without any participation of its central processing unit (CPU).
The BSP interrupts to CPU are generated after filling halves of the buffer. This machanism makes it
possible to effectively cooperate with multichannel ADCs and DACs or to accumulate samples for FFT
analysis. The described features, such as the HPI and the BSP, can substantially simplify the audio digital
signal processing system (cf., Fig. 27.18) [25,28].
Floating-point DSPs, with the support for the IEEE-754 standard of 32-bit floating-point format, are
based on new architecture concepts in order to guarantee a very high computational efficiency. Among
these concepts are:
• Texas Instruments’ VelociTI, which is an advanced very long instruction word (VLIW) architecture
[51],
• Analog Devices super Harvard architecture (SHARC) with a single instruction multiple data
(SIMD) facility [1].
Effective utilization of these highly parallel architectures needs an efficient C-compiler and an assembly
optimizer.
Comparison of selected fixed- and floating-point DSP processors is presented in Tables 27.2 and 27.3
[1,33,50,51].
© 2002 by CRC Press LLC
TABLE 27.2 Main Features of Fixed-Point DSPs
Processor Family
Bus
Interface (bits)
Instruction
Rate (MHz) Core MIPS
RAM
(bits)
ROM
(KWords)
ADSP-218x 16 33−75 33−75 128 K−1.6 M —
DSP56300 24 66−160 66−160 120 K−1.2 M 0−80
DSP56600 16 60−104 60−104 384 K−1.2 M 2−128
TMS320C54x 16 40−160 30−532 80 K−3.1 M 0−48
TMS320C55x 16 160−200 320−400 2.5 M 16
TMS320C62x 32 150−300 1200−2400 1−7 M —
TMS320C64x 32 400−600 3200−4800 8.5 M —
Host
computer
DSP processor
CPU
HPI Internal BSP
memory
FIGURE 27.18 A digital audio signal processing system.
multichannel
audio codec