U. Glaeser

FIGURE 5.17
Looking forward to the future of multithreaded processors, the pace of change makes for rich opportunities
and also for great challenges. Although it is difficult to precisely predict where this field will go,
this final section seeks to outline some of the key areas of development in multithreaded processors.
Whatever technological breakthroughs occur and whatever directions the market takes, the fundamental
issues addressed in the “Parallel Processing Software Framework” section will still apply. The realization
of multithreaded processors will still rest upon good techniques to perform thread selection, inter-PE
communication, and synchronization. The core techniques for addressing these issues will remain valid;
however, the way that they are employed will surely change as the critical parameters of clock speeds and
wire delays continue to change.
It is difficult to obtain good performance without having complexity somewhere in the hardwaresoftware
multithreaded system! In a high-performance multithreaded processor, the complexity could be
at the static partitioning side (programming or compiler), at the dynamic partitioning hardware side, or at
the PE interconnect side. Figure 5.17 illustrates this concept. To support hardware scalability, complexity
at the dynamic partitioning hardware and the PE interconnect act as hurdles. In the long run, as more
transistors are integrated into a processor chip, it can be expected that the number of PEs would be scaled up.
However, the trend towards higher clock rates will make it more difficult to support complexity in the
2
dynamic partitioning hardware and in the PE interconnect. Thus, the end result of the trends in high
transistor count and high clock rates (which encourage multithreading/multiprocessing) is a shift towards
doing more and more things statically, as opposed to dynamically. This means that program partitioning
will eventually be done only at compilation time, and perhaps more and more at programming time.
To Probe Further
Multiprocessing has been around for a long time, and so naturally the computer literature has an
overabundance of articles and textbooks on this subject. The multiprocessing community consists of
different camps, which often use different terminology for the same concepts. This lack of consensus
makes it somewhat difficult to merge the ideas presented in different papers or books. Nevertheless, we
© 2002 by CRC Press LLC
Multiscalar
Superthreading
Static Partitioning Complexity
(compilation and programming)
Dynamic Partitioning Complexity
(mostly logic delays)
SpMT processor
Complexity in multithreading/multiprocessing.
Trace processor
DMT
Difficulty in Scaling Up
the number of PEs
PE Interconnect Complexity
(mostly wire delays)
Superscalar
2
Although it is possible to pipeline a crossbar interconnect so that it can accept new requests every cycle, the long
inter-PE latency that it causes would increase the number of clock cycles required to execute a program, compared
with what is obtained with scalable interconnects [27].