U. Glaeser

The static components relate to the sensitivity to the DC value of the supply or substrate voltage. The static
noise sensitivity can predict the noise response for all but the high-frequency components of the supply and
substrate noise. The dynamic components relate to the extra sensitivity to a sudden change in the supply or
substrate voltage that the static components do not predict. The effect of the dynamic components increases
with increasing noise edge rate. For PLLs, the dynamic noise sensitivity typically has a much smaller overall
impact on the supply and substrate noise response than the static noise sensitivity; however, for DLLs, the
dynamic noise sensitivity can be more significant than static noise sensitivity. Only static supply and substrate
noise sensitivity are considered in this chapter.
Minimizing Supply Noise Sensitivity
All VCDL and VCO circuits will have some inherent sensitivity to supply noise. In general, supply noise
sensitivity can be minimized by isolating the delay elements used within the VCDL or VCO from one of
the supply terminals. This goal can be accomplished by using a buffered version of the control voltage
as one of the supply terminals; however, this technique can require too much supply voltage headroom.
The preferred and most common approach is to use the control voltage to generate a supply independent
bias current so that current sources with this bias current can be used to isolate the delay elements from
the opposite supply.
Supply voltage sensitivity is directly proportional to current source output conductance. Simple current
sources provide a delay sensitivity per fraction of the total supply voltage change ((dt/t)/(dVDD/VDD)), of
about 10%, such that if the supply voltage changed by 10% the delay would change by 1%. This level of
delay sensitivity is too large for good jitter performance in PLLs. Cascode current sources provide an
equivalent delay sensitivity of about 1%, such that if the supply voltage changed by 10% the delay would
change by 0.1%, which is at the level needed for good jitter performance, but cascode current sources can
require too much supply voltage headroom. Another technique that can also offer an equivalent delay
sensitivity of about 1% is replica current source biasing [9]. In this approach, the bias voltage for simple
current sources is actively adjusted by an amplifier in a feedback configuration to keep some property of
the delay element, such as voltage swing, constant and possibly equal to the control voltage.
Once adequate measures are taken to minimize the current source output conductance, other supply
voltage dependencies may begin to dominate the overall supply voltage sensitivity of the delay elements.
These effects include the dependencies of threshold voltage and diffusion capacitance for switching
devices on the source or drain voltages, which can be modulated by the supply voltage. With any supply
terminal isolation technique, all internal switching nodes will have voltages that track the supply terminal
opposite to the one isolated. Thus, these effects can be manifested by devices with bulk terminals
connected to the isolated supply terminal. These effects are always a problem for substrate devices with
an isolated substrate-tap voltage supply terminal, such as for NMOS devices in an N-well process with
an isolated negative supply terminal. Isolating the well-tap voltage supply terminal avoids this problem
since the bulk terminals of the well devices can be connected to their source terminals, such as with
PMOS devices in an N-well process with an isolated positive supply terminal. However, such an approach
leads to more significant substrate noise problems. The only real solution is to minimize their occurrence
and to minimize their switching diffusion capacitance. Typically, these effects will establish a minimum
delay sensitivity per fraction of the total supply voltage change of about 1%.
Supply Noise Filters
Another technique to minimize supply noise is to employ supply filters. Supply filters can be both passive,
active, or a combination of the two. Passive supply filters are basically low-pass filters. Off-chip passive filters
work very well in filtering out most off-chip noise but do little to filter out on-chip noise. Unfortunately,
on-chip filters can have difficulty in filtering out low-frequency on-chip noise. Off-chip capacitors can easily
be made large enough to filter out low-frequency noise, but on-chip capacitors are much more limited in
size. In order for the filter to be effective in reducing jitter for both DLLs and PLLs, the filter cutoff frequency
must be below the loop bandwidth.
© 2002 by CRC Press LLC