15.01.2013 Views

U. Glaeser

U. Glaeser

U. Glaeser

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

FIGURE 2.23 Different configurations of a DRAM cell: (a) 4-transistor DRAM cell, (b) 3-transistor DRAM cell,<br />

(c) 1-transistor DRAM cell.<br />

on the charge stored on its gate capacitance. Two more transistors are contained in each cell, one used as<br />

read access switch and the other used as write access switch. This cell is faster than the 4-transistor DRAM<br />

cell; however, every cell needs two control and two I/O (bit) lines making the area advantage insignificant.<br />

The widely popular DRAM cell is the single transistor DRAM cell shown in Fig. 2.23(c). It stores data<br />

as charge in an explicit capacitor. There is also one transistor which is used as the access switch. This<br />

structure consumes significantly less area than a static RAM cell. The cell has one control line (word<br />

line) and one data line (bit line). The cells can be selected using the word line, and the charge in the<br />

capacitor can be modified using the bit line.<br />

Read Only Memories (ROMs)<br />

ROM arrays are simple memory circuits, significantly simpler than the RAMs, which we discussed in the<br />

preceding section. A ROM can be viewed as a simple combinational circuit, which produces a specified<br />

output value for each input combination. Each input combination corresponds to a unique address or<br />

location. Storing binary information at a particular address can be achieved by the presence or absence<br />

of a connection from the selected row to the selected column. The presence or absence of the connection<br />

can be implemented by a transistor. Figure 2.24 illustrates a 4 × 4 memory array. At any time, only one<br />

word line among A1, A2, A3, and A4 is selected by the ROM decoder. If an active transistor exists at the<br />

cross point of the selected row and a data line (D1, D2, D3, and D4), the data line is pulled low by that<br />

transistor. If no active transistor exists at the cross point, the data line stays high because of the PMOS<br />

load device. Thus, absence of an active transistor indicates a “1” whereas the presence of an active transistor<br />

indicates a “0”.<br />

ROMs are most effectively used in devices, which need a set of fixed values for operation. The set of<br />

values are predetermined before fabrication and a transistor is made only at those cross-points where<br />

one is desired. If the information that is to be stored in the ROM is not known prior to fabrication, a<br />

transistor is made at every cross-point. The resulting chip is a write-once ROM. The ROM is programmed<br />

© 2002 by CRC Press LLC

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!