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U. Glaeser

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FIGURE 10.83 A column circuit.<br />

FIGURE 10.84 A write circuit.<br />

Write Circuit<br />

In the previous sub-section, a simple and fast circuit was presented. The write N transistor (and write select<br />

transistor) are large enough to drive the highly capacitive bit line down and overcome the P pull-up transistor<br />

inside the memory cell in the available write time. In that circuit the bit line is not driven to “1”. This is<br />

because the bit line can not write a “1” to the memory cell and the bit line is already pre-charged to “1”.<br />

To make sure that the bit line maintains the pre-charge value or if the pre-charge is not complete prior<br />

to write, to save time, the write circuit must drive the “1” side also. Figure 10.84 is a more complex write<br />

circuit that has only one N transistor (in series with the N column select transistor) and drives the high<br />

side as well. During the read cycle, this circuit is in tri-state, so same column select might be used for<br />

both read and write. Wen signal is either the write enable signal or a derivation of it.<br />

Sense Amplifier<br />

The sense amplifier is the last element considered in the column. In a read operation the bit lines are<br />

pre-charged first. Then a word line is activated to let the ND transistor in the cell pull either Bit or Bit#,<br />

depending on the data stored in the cell, down. The bit line is highly capacitive and the transistors in<br />

the memory cell are small for density purpose, so it may take a long time for the cell to completely<br />

discharge the bit line. The common practice is to let the cell develop only a limited differential voltage,<br />

about ∼100 mV, on the bit lines and amplify it by a sense amplifier. Thus, reducing and matching the bit<br />

line capacitance is important for a fast and correct read. Power consumption of a memory is also mainly<br />

determined by the bit line capacitance.<br />

Bit line capacitance components, contributed by each memory cell, include junction capacitance, bit<br />

line to bit line coupling, bit line to word line, and bit line to substrate capacitance. Thus, each cell connected<br />

© 2002 by CRC Press LLC<br />

Wen<br />

Bit Bit#<br />

din din#<br />

Readsel [1:0]<br />

Writesel [1:0]<br />

Pre-charge Pre-charge<br />

p<br />

din#[0] din[0] din#[1] din[1]<br />

Bit Bit#<br />

Sense amplifier

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