U. Glaeser

FIGURE 2.28 Comparison of CMOS logic with PTL.
FIGURE 2.29 Comparison for 2-input XOR logic.
capacitance, and so on. On the other hand, when “1” is input, the nMOS transistor becomes conductive
and the pMOS transistor becomes nonconductive in turn. Cout is then discharged, and the output is
pulled down to Gnd. Thus, “0” is output, and inverter operation is achieved. As shown here, in the CMOS
circuit nMOS and pMOS transistors complementarily perform the pull-up and pull-down operations,
respectively. This complementary operation allows the logic signal to swing fully from Vdd to Gnd, resulting
in a high noise margin. As a result, CMOS circuits are widely used in VLSI chips, such as microprocessors.
As an alternative to CMOS logic, pass-transistor logic (PTL) has recently been getting much attention.
This is because well-constructed PTL can provide a logic circuit with fewer transistors than the corresponding
CMOS logic circuit. In the PTL circuit, one nMOS transistor can perform both the pull-up
and pull-down operations by utilizing not only the gate but also the drain/source as signal terminals, as
shown in Fig. 2.28(b) [1]. Here, the signal connected to the gate of the transistor (B in this figure) is called
the control signal, and the signal connected to the drain/source (A in this figure) is called the pass signal.
In PTL, logic operation is performed by connecting and disconnecting the input signal to the output.
For example, in this figure, when the control signal is set to “0”, the nMOS transistor becomes nonconductive.
However, when the control signal is set to “1”, the transistor becomes conductive, pulling
the output up or down according to the input voltage, and the input signal is then transmitted to the
output. Thus, PTL is also called a transmission gate.
PTL is often used to simplify logic functions. For example, Fig. 2.29 shows a comparison of PTL and
CMOS circuits for 2-input XOR logic, Out = A B + AB.
PTL provides this XOR logic circuit with only
two transistors, while the CMOS circuit requires six transistors. (To generate complementary signals
for A and B, an additional four transistors in two inverters are required for both circuits.) This simplification
ability of PTL is effective not only for reducing chip size, but also for enhancing operating
speed and reducing power consumption. This is because the decrease in the number of transistors
reduces the total capacitance in the circuit, which must be charged and discharged for the logic operation,
thus wasting power and causing delay. In addition, the pMOS-free structure of the PTL is also advantageous
in terms of operating speed and power consumption. This is because the capacitance of a pMOS
transistor is twice as large as that of an nMOS transistor due to the wider size required by its inferior
current characteristics. The lack of a pMOS transistor thus enables lower capacitance, resulting in both
faster speed and lower power.
Because of these advantages, PTL is preferably used in arithmetic units in microprocessors, in which
complex logic functions such as XOR are needed to implement adders and multipliers with highperformance
[2–8]. PTL is also used to implement D-type latches and DRAM memory cell to reduce
chip size or the number of transistors, as shown in Fig. 2.30.
© 2002 by CRC Press LLC
In
V dd
Gnd
(a) CMOS
Out
Cout
A
B
(b) PTL
Vdd A A
B
B
Out
A A
B
B
(a) CMOS
Out
Cout
Gnd
B
A
A
B
(b) PTL
Out
A
B
A
B