U. Glaeser

In order to obtain a more accurate power estimation result, the internal nodes have to be considered.
In taking the internal nodes of the logic gates into consideration, the overall total power consumption
equation is modified to
© 2002 by CRC Press LLC
P total
i=1
(20.2)
where m is the number of internal nodes in the ith logic gate. Note that output node voltages can only
have two possible values: V supply and GND; however, each internal node voltage can have multiple possible
values (V j) due to charge sharing, and threshold voltage drop. In order to accurately estimate power
dissipation, we should be able to accurately estimate the switching activities of all the internal nodes of
a circuit.
20.3 Probabilistic Technique to Estimate Switching Activity
Probabilistic technique has been used to solve the strong input pattern dependence problem in estimating
the power consumption of CMOS circuits. The probabilistic technique, based on zero-delay symbolic
simulation, offers a fast solution for calculating power. The technique is based on an algorithm that takes
the switching activities of the primary inputs of a circuit specified by the users. The probabilistic analysis
relies on propagating the probabilistic measures, such as signal probability and activity, from the primary
inputs to the internal and output nodes of a circuit.
To estimate the power consumption, probabilistic technique first calculates the signal probability
(probability of being logic high) of each node. The signal activity is then computed from the signal
probability. Once the signal activity has been calculated, the average power consumption can then be
obtained by using Eq. (20.2).
The primary inputs of a combinational circuit are modeled to be mutually independent strict-sensestationary
(SSS) mean-ergodic 1-0 processes [3]. Under this assumption, the probability of the primary
input node x to assume logic high, P(x(t)), becomes constant and independent of time, and denoted by
P(x), the equilibrium signal probability of node x. Thus, P(x) is the average fraction of clock cycles in
which the equilibrium value of node x is of logic high.
The activity at primary input node x is defined by
where n x is the number of time the node x switches in the time interval of (−T/2, T/2). The activity A(x)
is then the average fraction of clock cycles in which the equilibrium value of node x is different from its
previous value (A(x) is the probability that node x switches). Figure 20.5 illustrates the signal probability
and activity of two different signals.
FIGURE 20.5 Signal probability and activity.
1
=
n
∑
2
2
⎛Vsupply Vj ⎞
⎜------------- ⋅ Cloadi ⋅ Ai + ----- ⋅ Cinternalj ⋅ Aj 2 ∑
⎟
⎝ 2
⎠
nx( T)
lim -----------n
→ ∞ T
Clock Cycle:
m
j=1
2 3 4 5 6 7 8 9 10
P = 0.5
A = 0.6
P = 0.5
A = 0.2