U. Glaeser

Finally, because the main task of network devices is to move packets from one interface to another,
efficient data movement is of paramount importance. Because most packet buffer memory is implemented
in DRAM, it is essential to exploit the fast access mode in modern DRAM chips to keep up with
the line rate. In addition, it should support multiple DMA channels to allow multiple data transfer
transactions to proceed in parallel without the attention of network processors.
Example Network Processors
Intel’s Internet exchange architecture (IXA) [6] includes an IXE component as the switching fabric, an
IXF component for framing and formatting, an LXT component for physical-layer processing, and an
Internet exchange processor (IXP) for packet processing. The IXP consists of a StrongARM core, six
microengines and interfaces with the SRAM, SDRAM, the PCI bus, and a proprietary bus, the IX bus.
The StrongARM core performs such supervisory processing as maintaining the routing table. Each of
six microengines is a RISC core augmented with special instructions optimized for network processing
such as bit extraction, table lookup, and single-cycle shifting, and with support for hardware multithreading.
Each microengine has four program counters that allow four parallel threads to time-share a
microengine’s data path. There are two banks of single-ported general-purpose registers for ALU operations,
and four single-ported transfer registers to read/write SRAM and SDRAM. The IX bus allows the
IXPs to interface with IXFs and IXEs, and supports 5 Gbps at 80 MHz.
Agere’s PayloadPlus architecture [9] includes a fast pattern processor (FPP), a routing switch processing
(RSP), an agere system interface (ASI), and a functional programming language (FPL) for programming
the FPP and RSP. The FPP sits between the physical interface and the RSP, and performs packet
re-assembly, protocol recognition and associated computation, and calculation of checksums and CRC.
The FPP is based on a pipelined and multithreaded architecture. It allocates a thread and a context to
process each incoming packet, and operates on one 64-byte block at a time, each in the associated packet’s
context. To program the FPP, system designers use a declarative programming language, FPL, to specify
the set of protocols to recognize and the set of actions to take for each specified protocol. Programs for
the FPP are represented as trees, where nodes correspond to pattern recognition functions and leaves as
actions. The RSP sits between the FPP and the switch fabric controller, and consists of three VLIW
engines: Traffic Management Compute engine that enforces packet discarding policies and maintains
queue statistics, Traffic Shaper Compute engine that ensures QoS and CoS for each connection queue,
and Stream Editor Compute engine that performs necessary packet modifications. These three engines
work on each packet together as a linear pipeline. The ASI interfaces with the host processor for
configuration and program download, and in addition coordinates the data movement between the FPP
and RSP.
C-Port’s digital communications processor (DCP) [10] includes 16 channel processors (CP), five specialized
processors, and a 160 Gpbs internal bus. Each CP interfaces with the physical link interface, and
consists of a RISC core and two serial data processors (SDP). SDPs perform low-level bit manipulation task
whereas the RISC core performs such high-level task as packet scheduling and traffic statistics collection.
The five specialized processors perform classification table access, packet buffering, routing table look-up,
interfacing with the switch fabric, and supervisory processing. C-Port supports a special communications
programming interface called C-Ware to simplify system designers’ task of programming DCP.
Conclusion
In this chapter section, we present the set of tasks that a modern network processor needs to perform,
describe a set of architectural features specifically designed for network packet processing, and survey
several commercial network processor architectures as examples. Most of existing network processors
include special instructions to speed up packet processing, and use a parallel multithreaded architecture
to exploit multiple levels of parallelism; however, these architectures cannot scale to OC768 link rate and
© 2002 by CRC Press LLC