U. Glaeser

FIGURE 31.4
bits known as inter-symbol interference (ISI). As data rates increase beyond gigabits per second, the
design of transmitters and receivers must incorporate additional filtering to compensate for this low-pass
filtering.
Methods of Signaling
The characteristics of the transmission medium influence the trade-off between various signaling methods.
In DRAM or backplane applications where a data word connects between multiple chips, multi-drop busses
save considerable pins over point-to-point connections; however, each drop of a bus structure introduces
a splitting of a transmission line that causes reflections and increases noise. A similar trade-off exists with
differential and single-ended signaling. Differential signaling is more robust to common-mode noise by
using the second wire as the explicit image current path. A third trade-off involves whether or not signaling
occurs in both directions on a pin simultaneously (full-duplex). Typically, an I/O link contains both a
transmitter and a receiver on each end. Only one pair is operating at one time (half-duplex). Operating
full-duplex halves the number of pins but degrades the signal amplitude and increases noise because the
receiver must now compensate for the transmitted values. All three of these common choices are trading
between the number of I/O pins and the signal-to-noise ratio (SNR). For high performance, system designers
often opt for the more expensive options of point-to-point and differential links that are half-duplex. Some
designers use single-ended signaling that has an explicit and dedicated ground pin for a signal’s image
current since perfectly differential structures are difficult to maintain in a PCB environment.
The following sections focus on the design of high-performance link circuitry in a high-performance
system of point-to-point links. Many of the design techniques are applicable to busses and bidirectional
links as well.
31.2 Transmitters
Transmitters convert the digital bits into analog voltages. Figure 31.4 illustrates the major pieces of a
transmitter. Prior to the conversion by the output driver, transmitters commonly synchronize the data
to that of a stable, noise-free clock so the resulting waveform has well-defined timing. Because I/Os often
operate at a higher rate than the on-chip clock, the synchronization also multiplexes the data. The simplest
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and most commonly used is 2:1 multiplexing, using each half-cycle of the clock to transmit a data bit.
A pre-driver follows the multiplexing and provides any pre-conditioning of the data signal.
The output voltage range depends on the signaling specification. If the voltage range nears or exceeds
that of the on-chip supply voltage, the design must convert the voltage and ensure the reliability to the
over-voltage. In addition to protection against electrostatic discharge (ESD), transistors that are not built
© 2002 by CRC Press LLC
D Q
D Q
Transmitter components.
Mux
0
1
Pre-driver
clock
generation
Driver
To
Channel
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For memories, the 2:1 multiplexing is known as double-data rate (DDR). The duty cycle of the clock is critical
in guaranteeing a constant width of each bit. Even higher multiplexing has been demonstrated using multiple clock
phases [52].