15.01.2013 Views

U. Glaeser

U. Glaeser

U. Glaeser

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

FIGURE 6.6 Scope of register renaming.<br />

Scope of Register Renaming<br />

The scope of register renaming indicates how extensively the processor makes use of renaming. In this<br />

respect we distinguish between partial and full renaming. Partial renaming is restricted to one or to only<br />

a few instruction types, for instance only to FP-instructions. This incomplete form of implementation<br />

was typical for the introductory phase of renaming, at the beginning of the 1990s (see Fig. 6.1). Examples<br />

of processors using partial renaming are the Power1 (RS/6000), Power2, PowerPC 601, and the Nx586,<br />

as shown in Fig. 6.6. Of these, the Power1 (RS/6000) renames only FP-loads. As the Power1 has only a single<br />

FP-unit, it executes FP-instructions in sequence, so there is no need for renaming floating point register<br />

instructions. Power2 introduces multiple FP-units, consequently it extends renaming to all FP-instructions,<br />

whereas the PowerPC 601 renames only the Link and count register. In the Nx586, which includes an<br />

integer core, renaming is restricted obviously only to FX-instructions.<br />

Full renaming covers all instructions including a destination register. As Fig. 6.6 demonstrates, virtually<br />

all recent superscalar processors employ full renaming. Noteworthy exceptions are Sun’s UltraSparc line<br />

and Alpha processors preceding the Alpha 21264.<br />

Layout of the Rename Buffers<br />

Overview<br />

Rename buffers establish the actual framework for renaming. From their layout we point out three<br />

essential design aspects—the type and the number of the rename buffers provided as well as the number<br />

of the read and write ports, as shown in Fig. 6.7.<br />

Types of Rename Buffers<br />

The choice of which type of rename buffers to use in a processor has far reaching impact on the<br />

implementation of the rename process. Given its importance, we will outline the various design options.<br />

To simplify our presentation, we initially assume a common architectural register file for all data types<br />

processed. We later extend our discussion to the split register scenario that is commonly employed.<br />

© 2002 by CRC Press LLC<br />

Partial renaming<br />

Renaming is restricted<br />

to particular<br />

instruction types<br />

A few early superscalar<br />

processors, such as<br />

Power1 1<br />

Power2 2<br />

Power-PC 3<br />

Nx586 4<br />

Comments:<br />

1<br />

Scope of register renaming<br />

(RS/6000, 1990)<br />

(1993)<br />

601 (1993)<br />

(1994)<br />

Trend<br />

Full renaming<br />

Renaming comprises<br />

all eligible<br />

instruction types<br />

The indicated superscalar<br />

lines beginnig with<br />

PowerPC 603 (1993)<br />

PA 7200 (1995)<br />

Pentium Pro (1995)<br />

R10000 (1996)<br />

K5 (1995)<br />

MII (1997)<br />

Most notable exceptions<br />

are former<br />

Alpha processors and<br />

Sun's UltraSparc line<br />

The Power1 renames only FP-loads.<br />

2<br />

The Power2 extends renaming to all FP-instructions.<br />

3<br />

The Power PC 601 renames only the Link and count<br />

register<br />

4<br />

Since the Nx586 has an integer core, it renames only<br />

FX-instructions.

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!