U. Glaeser

drain omitted, its gate polysilicon over thin oxide omitted, and its threshold voltage increased to a value
greater than the gate address voltage. For example, an additional mask and implant are used to increase
the cell transistor’s threshold voltage to a value large enough that the transistor remains “off” (I D = 0)
when the address voltage is applied to its gate. Thus, with all programming approaches, when the memory
cell is addressed, those cell transistors that are operational conduct drain current, and those that are not
operational do not conduct drain current. The binary information is in the presence or absence of drain
current. Drain current is detected by the column read amplifier, and binary output voltages are created
for communication out of the memory function. The column read amplifier can be a differential amplifier
or a fixed reference comparator. MVL ROM uses multiple valued drain currents to represent the stored
MVL data. MVL and binary ROM architectures are essentially the same except for sensing the multiple
valued currents and the creation of the equivalent binary information for output out of the memory
function. Four-valued ROM [7–10] have been successfully used in commercial products.
Four-valued ROMs can be programmed during manufacture using two approaches. One approach
uses two additional masks and implants to create four possible memory cell transistor threshold voltages
[8,10]. Drain current is nonlinearly proportional to the difference between the applied address gate
voltage and the effective threshold voltage. Cell transistors with four possible effective threshold voltage
values can be of minimum size and thus produce twice the cell bit density possible with the binary
version. This approach uses additional processing steps and masks, and thus a more expensive fabrication
technology. Another approach uses four different cell transistor channel widths or width-to-length ratios
to set the four possible drain current values [7,9]. Drain current is directly proportional to the channel
width. The spacing within the array of memory cell transistors must accommodate the largest of the four
possible transistor sizes, and thus must be greater than that of the threshold programmable version. This
geometry-variable approach requires additional silicon area and provides a bit density less than the
threshold programmable approach, but greater than the binary version; however, no additional fabrication
steps or masks are necessary for this geometry-variable cell.
Detection and interpretation of the four-valued memory cell transistor’s drain current is an analogto-two-bit
digital conversion problem that has many solutions. Traditional analog-to-digital conversion
design issues must be considered and all conversion approaches can be used. A simple approach uses as
comparator threshold references three reference currents that lie between the four logical values of the
drain current. This common “thermometer” arrangement of three comparators produces simultaneously
three comparison results that are easily decoded into arbitrary two-bit binary output combinations. This
simultaneous comparison of the data drain current to the references is the fastest approach to detecting
the stored data. These column read amplifiers are more than twice as complicated as the binary versions.
Because the number of read amplifiers is much smaller than the number of memory cells, this increase
in the read amplifier overhead circuitry reduces only slightly the overall density improvement provided
by the bit density increase of the large array of four-valued memory cells. Overall, four-valued ROM
implementations reduce chip areas 30–40%. For example, in [7], a math co-processor uses a maskgate-area-programmable
quaternary ROM that provides an approximately 31% ROM area savings
compared to a binary ROM. No system speed penalty was incurred because the slower MVL ROM is
fast enough to respond within the time budgeted for ROM data lookup. In [9], the 256 K four-valued
ROM is said to have minimal speed loss due to careful design of the ROM architecture, the sense amp
operation, and the data decoder output circuit design. Chip area savings of this four-valued ROM is
approximately 30%.
Both programming approaches provide significantly increased bit density compared to binary ROM.
The speed of the four-valued ROM is inherently reduced because the increased complexity of the column
read amplifiers, the increased capacitance of the larger memory cell transistors, and the reduced drain
current created by the memory cell transistors with large threshold voltages. Designers have minimized
the speed penalty with thoughtful chip architecture design and careful transistor level circuit performance
optimization. The improved capabilities demonstrated in these four-valued ROM designs motivated the
use of four-valued data storage in the EEPROM and flash memories discussed next.
© 2002 by CRC Press LLC