U. Glaeser

FIGURE 21.13 (a) Clock-powered precharged and pass-transistor logic arranged in pipeline stages and (b) net
computation time within a cycle.
Precharged and pass-transistor clock-powered logic microsystems are built in similar ways. Each logic
block evaluates within a phase (Fig. 21.13(a)). Logic block outputs are latched at the same phase. Logic
blocks start computing when the input clock-powered signals are charged to V th. In order for the output
to be latched in time, computation should finish before the falling edge of the clock phase crosses the V th
voltage level (Fig. 21.13(b)). Therefore, precharged and pass-transistor logic blocks perform useful computations
for less than half of the cycle time. However, precharged logic blocks are not totally idle the rest
of the time, since these blocks are precharged during the phase in which they do not evaluate. Furthermore,
clock-powered signals drive only the first gate level of precharged logic blocks. Precharged gates inside the
logic blocks are arranged in domino form. During the evaluate phase, either the clock-powered block
inputs are pulsed or they remain at 0 V, depending on their values. Therefore, once the computation is
fired, these inputs are no longer needed. Thus, the energy return time of the pulsed inputs is totally hidden
because of the nature of domino precharged logic. On the other hand, clock-powered signals that drive
pass-transistor gates are required to remain valid throughout the entire computation time.
The way that static clock-powered logic is arranged into pipeline stages depends on the converters
that are used. Both static and dynamic dual-rail-input converters (i.e., DD and DS P2LC) can drive static
logic blocks directly. The inputs of these converters change once every cycle. Therefore, almost a full
cycle is allotted for the static logic blocks to compute (Fig. 21.14(a)), disregarding the converter latency.
Assuming that the inputs of the DS or DD converters are pulsed on ϕ 1, then the output of the static logic
block is latched at the end of ϕ 2 (Fig. 21.14(b)).
As illustrated earlier, single-rail-input dynamic P2LCs operate like precharged gates because they are
reset during the phase that their input is not valid. Therefore, the outputs of SD P2LCs are valid only
for one phase, i.e., the phase in which their inputs are valid. One way to arrange them in pipeline stages
is to latch their outputs, and then use the latch outputs to drive static logic blocks (Fig. 21.15(a)).
Essentially, the SD P2LC output is transmitted through the latch at the beginning of the phase and
remains stable when the phase goes away. The net computation time is as shown in Fig. 21.14(b).
Alternatively, SD P2LC outputs can drive static logic blocks directly and the outputs of the static logic
blocks can be latched at the end of the phase (Fig. 21.15(b)). This requires logic blocks to be split into
smaller pieces with half latency. Operation is similar to the precharged clock-powered logic, and the net
computation time is as shown in Fig. 21.13(b). The energy return time is totally hidden for static clockpowered
logic, since clock-powered signals are not needed when they have been converted to levels.
For low-power operation, the rise and fall times of the clock phases must be longer than the practically
obtainable minimum transition times. The consequence of stretching the rise time is that, within a clock
cycle, the logic will activate later than it would from a minimal-transition-time input signal. A consequence
© 2002 by CRC Press LLC
ϕ 2
Latch
ϕ1 ϕ1 ϕ2 ϕ2 ϕ1 CB
∧ϕ1 Prech./PT
Logic
Latch CB
∧ϕ2 Prech./PT
Logic
Latch
CB
V th
evaluates on ϕ 1
ϕ 1
t cph
1 cycle
(a)
(b)
evaluates on ϕ 2
ϕ 2
t cph