U. Glaeser

assigned, based on the subcircuit topology and the relative position of the driving transistor in the stack.
The result, which is rather a measure of the logical effort of the design, reflects to a first order the actual
speed of the circuit. Table 10.7 shows the three topologies used to match subcircuits. It corresponding to
single-, double-, and triple-transistor stack. Each transistor in the stack is assigned a propagation delay
normalized to a FO4 inverter delay, with increasing delays toward the bottom of the stack (closest to V DD
or V SS). The table provide NMOS versus PMOS delay (PMOS stack are 20% slower) and also skewed
versus complementary static logic. Details on the delay computation for each design is provided in the
“Appendix.”
Table 10.8 provides a summary of the timing characteristics for most of the flip-flops and latches studied
in this chapter section. The clocking scheme for latches is assumed to be complementary dual-phase.
Values are normalized to a FO4 inverter delay, unless otherwise indicated. The first column is the maximum
D-to-Q delay and is the value used to compute the pipeline overhead. The second and third column contain
the minimum CK-to-Q delay and the hold time, respectively. The fourth column represents the overall
pipeline overhead, which is determined according to Table 10.6. This establishes whether the latch delay
is paid once or twice or whether the clock skew is added or not to the pipeline overhead. The overhead
is expressed as a percentage of the cycle time, assuming that the cycle is 20 FO4 inverter delay, and that
the clock skew is 10% of the cycle. The fifth column represents the minimum propagation delay between
latches, or between flip-flops, required to avoid min-timing problems. It is computed according to
Table 10.6, and assuming that the clock skew is 5% of the cycle time. A smaller clock skew is assumed
© 2002 by CRC Press LLC
TABLE 10.7 Normalized Speed (FO4 Inverter Delay) of Complementary and Skewed
Logic, Where Top Refers to Device Next to Output, and Bottom to Device Next to V DD
or GND
Complementary Logic Skewed Logic
Stack Depth Input NMOS PMOS NMOS PMOS
1 Top 1.00 1.20 0.50 0.60
2 Top 1.15 1.40 0.60 0.70
Bottom 1.30 1.55 0.70 0.85
3 Top 1.30 1.55 0.70 0.85
Middle 1.50 1.80 0.80 0.95
Bottom 1.75 2.10 0.95 1.15
TABLE 10.8 Timing Characteristics, Normalized to FO4 Inverter Delay, for Various Latches and Flip-Flops
Latch/Flip-Flop Design
Max
D-to-Q
Min
CK-to-Q
Hold
Time
Pipeline
Overhead (%)
Min
Delay
Dual trans. gate latch w/o input buffer (Fig. 10.53(d)) 1.50 1.75 0.75 15 0.00
Dual trans. gate latch w/ input buffer (Fig. 10.53(e)) 2.55 1.75 −0.25 25.5 −1.00
Dual C 2 MOS latch (Fig. 10.55(b)) 2.55 1.75 0.75 25.5 0.00
Dual TSPC latch (Fig. 10.56(b) and Fig. 10.56(d)) 3.70 1.75 0.25 37 0.50
Master-slave flip-flop w/ input buffer (Fig. 10.60) 4.90 1.75 −0.25 34.5 −1.00
Master-slave flip-flop w/o input buffer (not shown) 3.70 1.75 0.75 28.5 0.00
C 2 MOS flip-flop (Fig. 10.61) 3.90 1.75 0.75 29.5 0.00
TSPC flip-flop (Fig. 10.62) 3.85 1.75 −0.05 29.2 −0.80
Sense-amplifier flip-flop (Fig. 10.63) 3.90 1.55 1.40 29.5 0.85
HLFF used as flip-flop (Fig. 10.68) 2.90 1.75 1.95 24.5 1.20
SDFF (Fig. 10.69) 2.55 1.75 2.00 22.7 1.25
Pulsed trans. gate latch (Fig. 10.66(a)) 2.55 1.75 3.70 12.7 2.95
Pulsed C 2 MOS latch (not shown) 2.55 1.75 3.70 12.7 2.95
Pulsed transmission-gate flip-flop (Fig. 10.67) 3.90 1.75 1.30 20.2 0.55
HLFF used as pulsed latch (Fig. 10.68) 3.90 1.75 1.95 19.5 1.20
Note: The clock cycle is 20 FO4 inverter delays. Clock skew is 10% of the clock cycle for max-timing, and 5% (1 FO4
delay) for min-timing.