U. Glaeser

46.3 Future of Scan: A Brief Forecast
Scan for Analog and Mixed Designs
Boundary-scan was originally developed for digital circuits and systems. The motivations to use BS for
analog designs is also true; however, in contrast to digital circuits and systems, analog components are
specified by a continuous range of parameters rather than binary values 0 and 1. A new standard is
coming called P1149.4. It consists in the development of a mixed signal test bus. The aim is to standardize
to several possible tests in the case of analog DUT: interconnect test, parametric test, and internal test.
Such tests should be fully compatible with the IEEE 1149.1 standard and helps in measuring the values
of discrete components such as pull-up resistors and capacitors. Consequently, P1149.4 can be seen as an
extension of IEEE 1149.1 where the BS cells presented above are replaced by analog boundary modules
(ABM) at the level of each analog functional pin. Such pins can be accessed via internal analog test bus.
Fig. 46.8 gives the structure of the P1149.4 bus.
As IEEE 1149.1 has proven its efficiency, P1149.4 is most likely a good DFT solution for analog circuits
and systems. Furthermore, its compatibility with the IEEE 1149.1 will simplify the test of mixed DUT.
For more details regarding the standard, please refer to [7].
RTL and Behavioral Scan
Scan techniques that have been presented until now have several drawbacks. First, they are highly related
to the used design tools and target libraries. Moreover, in case of highly complex DUT, a high computation
time is required because low-level descriptions (gate-level or lower) are considered. Furthermore, the
added logic does not take advantage of the global optimization of the design, which can be performed
by the used synthesis tools.
Recently, several techniques that improve the testability using high level descriptions [8-10], have been
proposed. For example in [9], a technique which inserts a partial scan using the B-VHDL (behavioral
VHDL) description has been presented. In [10], a technique that allows scan to be inserted at the B-VHDL
description of a DUT has been presented. This has many advantages. The scan insertion problem is
considered very early in the design process, which means that a fully testable design can be provided at
the behavioral level, i.e., before any structural information is known. Compared to approaches that
may include scan at the RTL or the logical level, inserting scan at the behavioral level is very promising
since it takes fully advantage of design validation and test generation tools that might operate at the
FIGURE 46.8
© 2002 by CRC Press LLC
Digital I/O
pins
Internal Test
Bus
Test Access
Port (TAP)
TDI
TD0
TMS
TCK
Structure of the P1149.4 bus.
Core
circuit
Test bus
interface circuit
Test control circuitry
TAP controller
Instruction register and decoder
AT1
AT2
Analog
Boundary
Module
(ABM)
Analog
Test Access
Port (ATAP)