U. Glaeser

6. Baskoro, E. and Morris, J., Fast adders in FPGAs, Technical Report TR2001-01, Centre for Intelligent
Information Processing Systems, University of Western Australia, 2001.
7. Xilinx, Inc., XC6200 Field Programmable Gate Arrays, 1997.
8. Guccione, S., List of FPGA-based computing machines, www.io.com/~guccione/HW_list.html, 1999.
9. Buell, D.A., Arnold, J.M., and Kleinfelder, W.J., Splash 2: FPGAs in a Custom Computing Machine,
IEEE Computer Society Press, California, 1996.
10. Vuillemin, J., et al., Programmable active memories: reconfigurable systems come of age, IEEE Trans.
on VLSI Systems, 4, 1, 56, 1996.
11. Moll, L. and Shand, M., Systems performance measurement on PCI Pamette, in IEEE Symp. on FPGAs
for Custom Computing Machines, Pocek, K.L. and Arnold, J., Eds., Napa Valley, CA, p. 125, 1997.
12. Cockshott, W.P., Barrie, P., McCaskill, G., and Milne, G.J., Realising massively concurrent systems
on the SPACE Machine, in Proc. IEEE Workshop on FPGAs for Custom Computing Machines, Buell, D.
and Pocek, K., Eds., IEEE Computer Society Press, 1993.
13. Milne, G.J., Reconfigurable custom computing as a supercomputer replacement, in Proc. 4th International
Conference on High-Performance Computing, Bangalore, India, p. 260, Dec. 1997.
14. Morris, J., Bundell, G.A., and Tham, S., A reconfigurable processor for Petri net simulation, in Proc.
HICSS-33, El-Rewini, H. and Helal, S., Eds., Maui, HI, 2000.
15. Tham, S., Achilles: High bandwidth, low latency interconnection for parallel processors, PhD Thesis,
Electrical and Electronic Engineering, University of Western Australia, 2001.
16. Motorola Semiconductor Products, MPC500, MPC800 microprocessors, http://e-www.motorola.
com/index.html, 2001.
17. Woodfill, J., von Herzen, B., and Zabih, R., Real-time stereo vision on the PARTS reconfigurable
computer, in 5th IEEE Symp on FPGAs for Custom Computing Machines, Pocek, K.L. and Arnold, J.,
Eds., Napa Valley, CA, p. 201, 1997.
18. Woodfill, J., von Herzen, B., and Zabih, R., Frame-rate robust stereo on a PCI board, http://www.cs.
cornell.edu/rdz/Papers/Archive/fpga.pdf, 1998.
19. Piacentino, M.R., van der Wal, G.S., and Hansen, M.W., Reconfigurable elements for a video pipeline
processor, in 7th IEEE Symp on Field-Programmable Custom Computing Machines, Pocek, K.L. and
Arnold, J., Eds., p. 82, 1999.
20. Shand, M. and Vuillemin, J., Fast implementation of RSA cryptography, in Proc 11th IEEE Symposium
on Computer Arithmetic, Windsor, Ontario, 1993.
21. Schneier, B. et al., Twofish: a 128-bit block cipher, http://www.counterpane.com/twofish-paper.html,
2001.
22. Elbirt, A.J. et al., An FPGA implementation and performance evaluation of the AES block cipher
candidate algorithm finalists, in The Third Advanced Encryption Standard Candidate Conference,
New York, April 13–14, 2000.
23. Chodowiec, P., Khuon, P., and Gaj, K., Fast implementations of secret-key block ciphers using mixed
inner- and outer-round pipelining, in 9th ACM Intl Symp on Field-Programmable Gate Arrays, Schlag,
M., Ed., Feb. 2001.
24. Paar, C. et al., An algorithm-agile cryptographic co-processor based on FPGAs, in Reconfigurable
Technology: FPGAs for Computing Applications, Proc. SPIE, Schewel, J. et al., Eds., 3844, p. 11, 1999.
25. Huang, W.-J., Saxena, N., and McCluskey, E.J., A Reliable LZ data compressor on reconfigurable
coprocessors, in 8th IEEE Symposium on Field-Programmable Custom Computing Machines, Pocek,
K.L. and Arnold, J., Eds., p. 175, 2000.
26. Andraka, R., A survey of CORDIC algorithms for FPGA based computers, in Proc 6th Intl Symp on
Field Programmable Gate Arrays, Kaptanoglu, S., Ed., p. 191, 1998.
27. Hoang, D.T., Searching genetic databases on Splash 2, in Buell, D.A., Arnold, J.M., and Kleinfelder,
W.J., Splash 2: FPGAs in a Custom Computing Machine, IEEE Computer Society Press, California, 1996.
28. Gunther, B.K., Milne, G.J., and Narasimhan, L., Assessing document relevance with run-time reconfigurable
machines, in 4th IEEE Symposium on FPGAs for Custom Computing Machines, p. 10, 1996.
© 2002 by CRC Press LLC