U. Glaeser

FIGURE 21.6 (a) E-R latch, (b) timing diagram when D in is high, and (c) symbol that denotes a clocked buffer
pulsed on ϕ D.
Without loss of generality, the latch-stage output DinL
is assumed in negative polarity. The latch stage
and the inverter I1 are powered from a dc supply with voltage Vdd. The gate of transistor M1 connects to
a dc supply with voltage Viso. This dc supply dissipates no power since it is connected only to passtransistor
gates. Viso is equal to Vdd + VtE, where VtE is the nFET effective threshold voltage, so that the
boot node bn can be charged close to the maximum possible voltage Vdd. During ϕL, Din is stored on the
gate capacitance of M2 (the boot node). If Din is low, then the clamp transistor M3 holds the output to
ground. If Din is high (Fig. 21.6b), then bn charges to Vdd through the isolation transistor M1. When the
positive edge of ϕD occurs, the voltage of bn bootstraps to well above Vϕ due to the gate-to-channel
capacitance of M2. Then the output charges to Vϕ from the clock line ϕD through the bootstrap transistor
M2. Charge returns to the clock line through the same path at the end of ϕD. The timing sketch of
Fig. 21.6(b) indicates Vdd (i.e., the voltage that Vbn is charged to) as being less than Vϕ. Although this is
possible and happens in certain cases, it is not necessary. Voltages Vdd and Vϕ can be decided based on the
logic style and the system requirements.
The dc supply Viso is introduced so that the transistor M2 is always actively driven. Phase ϕL could be
used instead of Viso to drive the transistor M1 [21]. If this were the case, when ϕD occurred and bn was
at 0 V, the voltage of bn would bootstrap to above 0 V and short-circuit current would flow from ϕD to
ground through the transistors M2 and M3. The E-R latch is small in area. The size of M1 is made small to minimize the parasitic capacitance of
node bn. M3 can also be small since it only clamps the output to ground to avoid coupling to the output
when bn is 0 V. It does not discharge the load capacitance. On the other hand, the size of the device M2 is critical. Two criteria are used for sizing M2. First, the ratio of the gate capacitance of M2 to the parasitic
capacitance of the node bn should be large enough to allow the voltage of bn to bootstrap to at least
Vϕ + VtE. This criterion applies for small capacitance loads and/or slow systems. Second, the transistor M2 should be large enough to meet the system frequency and energy savings specifications. A detailed
analytical model for obtaining the on-resistance Rb of the bootstrap transistor has been derived elsewhere
[22,23]. This model can be used for sizing these transistors based on the load capacitance CL and the
desired RbCL/Ts ratio for a given switching time Ts. The key feature of E-R latches for low power is that they pass clock power. Therefore, an energyefficient
charge-steering device is essential. In addition to a bootstrap transistor, other charge-steering
topologies are a nonbootstrapped pass transistor and a transmission gate (T-gate). The pass transistor
would require its gate to be overdriven, which would impose constraints on the allowable voltage levels.
The pass-transistor gate would be powered from the dc supply Vdd, and Vdd would need to be at least
Vϕ + VtE. Otherwise the output would not be fully charged to Vϕ. The T-gate would fully charge the
output, but it would require a pFET connected in parallel to the nFET; however, since pFETs carry less
current per unit gate area than nFETs, the combined nFET and pFET width of the T-gate would be larger
© 2002 by CRC Press LLC
D in
ϕ L
Latch
D inL
I 1
(a)
the
V
boot
iso
node
(bn)
M1 ϕ D
M 2
M 3
V out
ϕ D
C L
in out
CB
(c)
V ϕ
0
V ϕ
0
ϕ L
Vbn Vout (b)
ϕ D