U. Glaeser

FIGURE 3.7 V REG voltage regulator circuit.
level and V R are compared by an operational amplifier whose output controls V REG. When the monitored
V REG level is lower than the target level V R, the output potential of the op-amp rises, which increases the
current in the V REG voltage regulator and pushes the potential of V REG up. On the contrary, when the
monitored V REG level is higher than the target level V R, the potential of V REG is controlled to go down.
This way, the op-amp adjusts the V REG level such that the LS-APD-ECL circuits which are hooked up to
the V REG lines have the same I SS(L) as that in the replica circuit. The stability of the negative feedback loop
in the V REG regulator can be secured by a common method of compensation, narrow banding. A phase
margin of 90 degrees is preserved when an external capacitor of 0.1 µF is put on the V REG lines.
The voltage regulator can be implemented in an I/O slot of a chip from which V REG lines are provided
to internal cells. Parasitic resistance along the V REG lines, however, produces a significant voltage drop
when large dynamic pull-down current from all the LS-APD-ECL cells is concentrated in one regulator.
Therefore, a local current-source is provided in each LS-APD-ECL gate to distribute the pull-down current.
Parasitic capacitance between the two lines, V REGC and V REGB, helps improve the transient response of the
local current-source.
In Fig. 3.8 are depicted simulated dependence of the output voltages, V OH and V OL; the steady-state
currents, I SS(H) and I SS(L); and the circuit delays, T pLH and T pHL, on power supply voltage, temperature,
and the number of the LS-APD-ECL gates. It is assumed in the simulation study that 8 mm by 8 mm
chip area is covered by 16 by 16 mesh layout for V REGC lines of 2 µm width. The equivalent resistance
between two far ends of the meshed V REG lines is estimated to be 20 Ω. Even at the tip of the meshed
V REG lines, the tracking error can be controlled within a range of 30 mV, which is small enough to be
within the allowed error range. Since the V REG voltage regulator circuit controls the output voltage swing
and the bias current of QU and QD constant, variation of the circuit delay can be kept very small even
under the large changes in circuit conditions.
Simulated transient response of the LS-APD-ECL circuit with the V REG voltage regulator circuit is
depicted in Fig. 3.9 when 1100 LS-APD-ECL gates are hooked up to the V REG voltage regulator, and 100
gates are switching simultaneously. Small bounce noise is observed at the V REG lines, which, however,
does not affect V OL nor V OH of staying gates, nor does it degrade the switching speed. The broken line
in the figure is the output waveform of a gate placed near the V REG voltage regulator, while the solid line
is for a gate placed in the far end of the V REG lines. Very little difference can be observed between them.
Layout of inverter gates with the conventional ECL and the LS-APD-ECL circuits are depicted in
Fig. 3.10. They both are implemented on an ECL gate array [8]. The V REG voltage regulator is implemented
in an I/O slot from which V REG lines are provided to internal cells. In a 9.6-mm by 9.5-mm chip, 24 types
of gate chains are implemented for three loading conditions (fanout one plus metal interconnection of
© 2002 by CRC Press LLC