Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.6.6 ECC Control Register - ECCRThis register programs the MCU error correction and detection capabilities. The configurationdepends on the application’s needs but a typical configuration is:• Enable multi-bit error reporting• Enable single-bit error reporting• Enable single-bit error correctingWhile there are separate bits for single-bit and multi-bit error reporting, when either is enabled,both are enabled.For more details, see Section 3.2.4, “Error Correction and Detection” on page 3-27 andSection 3.4, “Interrupts/Error Conditions” on page 3-41.Table 3-23.ECC Control Register - ECCRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address1534HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:03 000 0000H Reserved02 0 2 0 = Disable single bit error correctionSingle Bit Error Correction Enable: Enables or disables the correction of a single bit error.1 = Enable single bit error correction01 0 2 0 = Disable multi-bit error reportingMulti-Bit Error Reporting Enable: Enables or disables the reporting of a multi-bit error condition.1 = Enable multi-bit error reporting00 0 2 0 = Disable single bit error reportingSingle Bit Error Reporting Enable: Enables or disables the reporting of a single bit error condition.1 = Enable single bit error reportingDeveloper’s Manual 3-51