Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.6 Multi-Transaction TimerThe CIU has an associated Multi-Transaction Timer (MTT) in the Internal Bus Arbiter. Whenprogrammed properly, the MTT allows for a guaranteed quantum of time for the CIU. See Chapter7, Intel ® 80312 I/O Companion Chip Arbitration.8.6.1 Performance MonitoringThe Performance Monitoring Unit monitors various events related to CIU.See the Chapter 11, Performance Monitoring Unit for additional information.8.7 Interrupts and Error ConditionsThe CIU records error conditions that result from accesses initiated by the CIU on the Internal Bus.The errors are recorded in the CIU Interrupt Status Register (CIUISR).8.7.1 Master-AbortThere are two ways that the CIU can receive a Master-Abort from the Internal Bus:• Internal Bus Master-Abort: No target on the Internal Bus claims the transaction• PCI Master-Abort: The ATU, as a PCI master on behalf of the CIU, received a Master-Aborton the PCI bus and is returning the Master-Abort to the CIU during the read completionWhen an Internal Bus access initiated by the CIU receives a Master-Abort, the CIU records theMaster-Abort condition in the CIU Interrupt Status Register and signals an IRQ# interrupt to theIntel ® 80200 processor. Note that a Master-Abort received from the ATU is not recorded as aninternal bus Master-Abort in the CIU Interrupt Status Register.The PCI Master Abort is recorded in the PATUISR or SATUISR depending on which outboundATU window is accessed. The ATU generates an IRQ# interrupt to the Intel ® 80200 processor.When the ATU detects a Master-Abort on the PCI bus for a read access and the ATU returns theMaster-Abort to the CIU during the read completion.For read accesses, the CIU aborts the read request by asserting ABORT and DVALID signals onthe Intel ® 80200 processor bus, and clear the access from the Request Buffer. For write accesses,the CIU clears the access from the Request Buffer.Because writes are posted, the ATU is responsible for signalling an IRQ# interrupt to the Intel ®80200 processor when a PCI Master-Abort is received during a write access to the ATU.8-12 Developer’s Manual