Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.2.2 Secondary PCI Reset• asserts the secondary PCI bus reset signal S_RST#• resets the SATU• resets DMA channel 2• resets all Memory Mapped Registers in the SATU and DMA2• latches S_REQ64# to determine the secondary PCI bus interface width\Upon the assertion of P_RST#, theIntel ® 80312 I/O companion chip asserts the secondary PCIreset output (S_RST#). S_RST# remains asserted for the same period as P_RST#. The secondaryPCI arbiter is connected to the S_RST#. As with the primary PCI interface, the secondary PCIinterface is required to sample S_REQ64# on the rising edge of S_RST# to determine whether theIntel ® 80312 I/O companion chip is connected to a 64-bit or a 32-bit wide PCI bus. Since thesecondary PCI arbiter is integrated into the Intel ® 80312 I/O companion chip, the secondary arbiteris required to drive S_REQ64# on the rising edge of S_RST# based on the strapping option pin32BITPCI_EN#.RefertoChapter 7, “Intel ® 80312 I/O Companion Chip Arbitration” foradditional information.Secondary PCI reset is also available through the Extended Bridge Control register (EBCR) in thePCI to PCI Bridge Unit. The secondary PCI reset unit contains sideband signals from and to theSATU and DMA2. These sideband signals are used to ensure a graceful completion of these unitson the internal bus during the secondary PCI reset. Table 15-4 describes the behavior during asecondary PCI reset.Developer’s Manual 15-7