Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.4.3 ECC CheckingWhen enabled, the ECC logic uses the following ECC read algorithm. This algorithm corrects thedata before it's driven onto the internal bus. The ECC algorithm for a read transaction is:Read 64-bit data and 8-bit ECCCompute the syndromeif the syndrome 0 {ECC Error}determine error typeRegister the address where the error occurredif error is correctable {single bit}Correct dataSend corrected data to internal busInterrupt 80200 processor for software scrubbingelse {uncorrectable}if the read cycle is a part of a RMW cycleInterrupt the 80200 processor for uncorrectable error (MCISR[2])elseTarget-Abort the transactionWhen the MCU reads the ECC code from the memory subsystem, it is compared (XORed) with anECC that the MCU generates from the data read from the memory. The result is called thesyndrome. Table 3-13 shows how the MCU decodes the syndrome for SDRAM read cycles.Table 3-13.Syndrome DecodingError TypeSymptomNone The syndrome is 0000 0000.Single-BitNibbleDouble-BitThe syndrome contains an odd number of ones.One nibble of the syndrome contains 3 bits that are a “1” and the other nibble contains allzeroes. This error is uncorrectable.All other syndrome values. This error is uncorrectable.When decoding the syndrome indicates a double-bit or nibble error (see Table 3-13), thetransaction results in a target-abort. When an internal bus master detects a target-abort, the masterasserts IRQ# to the Intel ® 80200 processor. When during a write cycle, the internal bus master hasalready released the bus, the MCU sets bit 2 in the MCISR and the MCU interrupts the Intel ®80200 processor with an IRQ#.When the syndrome indicates a single-bit error, the H-Matrix (Figure 3-17)isusedtodeterminethebit error. For example when the syndrome was 1100 0001 (S[7:0]), the error is with bit 0 ofDQ[63:0]. To correct the error, the MCU inverts bit 0 before driving the data on the internal bus.Developer’s Manual 3-29