Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11.5 PCI-to-PCI Bridge Error SummaryTable 4-20 and Table 4-21summarize the bridges error reporting for PCI bus errors (parity andtransaction termination). The tables are in relation to the Primary and Secondary Status Registers.Each table details the corresponding registers error bit and the conditions that set the bit. ThePrimary and Secondary Bridge Interrupt Status Registers are also shown. These registers recordIntel ® 80200 processor interrupt status information.Note:When an external agent violates PCI protocol, PCI-to-PCI Bridge behavior may beunpredictable/undefined.Table 4-20. PSR Error Reporting Summary (Sheet 1 of 3)Error Bit in Primary StatusRegister (PSR)Detected Parity Error - Bit 15Data Parity Error Detected - Bit 8Error ConditionAddress Parity Error on PrimaryInterfaceUpstream Read Data Parity Erroron Primary BusDownstream Posted Memory WriteData Parity Error on Primary BusDownstream Delayed Write DataParity Error During Request Cycleon Primary Bus when Request isSeen with Bad Parity &Immediately CompletedDownstream Delayed Write DataParity Error During CompletionCycle on Primary Bus, Only whenError Occurred During RequestPhase of Transaction on PrimaryBus and Completion Request fromMaster Matches Initial RequestErrorUpstream Delayed Read DataParity Error on Primary BusUpstream Delayed Write DataParity Error During CompletionCycleonPrimaryBusUpstream Posted Memory WriteData Parity Error on the PrimaryBusQualifying Bit in PrimaryCommand Register(PCR Unless Otherwise Noted)N/AN/AN/APrimary Parity Error ResponseEnable must be SET- bit 6Primary Parity Error ResponseEnable must be CLEAR- bit 6Primary Parity Error ResponseEnable - bit 6Primary Parity Error ResponseEnable - bit 6Primary Parity Error ResponseEnable - bit 64-74 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-20. PSR Error Reporting Summary (Sheet 2 of 3)Error Bit in Primary StatusRegister (PSR)Signaled System Error - bit 14Master Abort - bit 13Target Abort (master) - bit 12Error ConditionAddress Parity Error on PrimaryInterfaceAddress Parity Error on SecondaryInterfaceDownstream Posted Memory WriteData Parity Error Which Occurs onSecondary Bus and Did Not Occuron Primary BusUpstream Posted Memory WriteData Parity Error Which Occurs onPrimary Bus and Did Not Occur onSecondary BusDownstream Posted Memory Writethat Receives a Target Abort onSecondary Bus and theTransaction is Not Currently Activeon the Primary InterfaceUpstream Posted Memory Writethat Receives a Target Abort onPrimary Bus and the Transaction isNot Currently Active on theSecondary InterfaceDownstream Posted Memory Writethat Ends in a Master Abort on theSecondary BusUpstream Posted Memory Writethat Ends in a Master Abort on thePrimary BusOneof8DiscardTimersExpireUpstream Delayed Read (memoryor I/O) Which Received a MasterAbort on the Primary BusUpstream Write (posted ordelayed) Which Received a MasterAbort on the Primary BusUpstream Delayed Read (memoryor I/O) Which Received a TargetAbort on the Primary BusUpstream Write (posted ordelayed) Which Received a TargetAbort on the Primary BusQualifying Bit in PrimaryCommand Register(PCR Unless Otherwise Noted)Primary Parity Error ResponseEnable - bit 6SERR# Enable - bit 8Secondary Parity Error ResponseEnable - bit 0 (BCR)SERR# Enable - bit 8SERR# Forwarding - bit 1 (BCR)Primary Parity Error ResponseEnable - bit 6Secondary Parity Error ResponseEnable - bit 0 (BCR)SERR# Enable - bit 8Primary Parity Error ResponseEnable - bit 6Secondary Parity Error ResponseEnable - bit 0 (BCR)SERR# Enable - bit 8SERR# Enable - bit 8SERR# Enable - bit 8Master Abort Mode - bit 5 (BCR)SERR# Enable - bit 8Master Abort Mode - bit 5 (BCR)SERR# Enable - bit 8Discard Timer SERR# Enable -bit 11 (BCR)SERR# Enable - bit 8N/AN/AN/AN/ADeveloper’s Manual 4-75
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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