Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-45. Bridge Control Register - BCR (Sheet 2 of 2)IOPAttributes15 12 8 4 0rv rv rv rv rw rc rw rw ro rw rw rv rw rw rw rwPCIAttributesrvrvrvrvrwrcrw rwrorw rwrvrw rw rw rwPCI Configuration Offset3E - 3FHIntel ® 80200 Processor Local Bus Address0000 103EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description05 0 2Master Abort Mode - This bit controls the bridge functionality whenever a Master-Abort terminationoccurs on either interface for transactions in which the bridge is the slave.When clear, reads will return all ones (32-bit or 64-bit depending on the PCI bus size of the initiatingmaster and in the 64-bit bus case on REQ64#/ACK64#) and write data will be accepted by the bridgeand discarded.When set, the bridge will signal a Master-Abort to the requesting master when the correspondingtransaction on the other side of the bridge terminates with a Master-Abort and the transaction has notyet been concluded (reads and non-posted writes). When the bit is set and the transaction on therequesting interface has completed (posted writes) then the bridge must assert P_SERR# on thePrimary interface (providing enabled in the PCR).04 0 2 Reserved.03 0 2VGA Enable - Modifies the bridge response to VGA compatible addresses. When set to a ‘1’, thisbitindicates that a VGA device is on the Secondary PCI bus. Therefore, the bridge positively decodes andforwards the following transactions downstream regardless of the value of the MBR/MLR, PMBR/PMLR,and IOBR/IOLR registers.Memory transactions addressing: 000A0000h-000BFFFFhI/O transactions addressing: 3B0h-3BBh and 3C0h-3DFhIn addition, the Secondary address decoder will block the forwarding of these I/O and Memorytransactions from Secondary to Primary.When set to ‘0’ the bridge will not forward VGA compatible memory and I/O addresses from theSecondary to the Primary PCI interface unless they are enabled for forwarding by the defined I/O andmemory address ranges.02 0 2ISA Enable - This bit modifies the bridges response to ISA I/O addresses. This only applies to I/Oaddresses that are defined by the bridge in IOBR and IOLR and are also in the first 64 Kbytes of PCIaddress space (0000.0000H - 0000.FFFFH)When set, the bridge will not forward from Primary to Secondary and I/O transactions addressing thelast 768 bytes in each 1 Kbyte block. In the opposite direction, I/O transactions will be forwarded up thebridge when the address the last 768 bytes in each 1 Kbyte block.01 0 2Secondary SERR# Enable - This bit controls the forwarding of Secondary interface S_SERR#assertions to the Primary interface. When this bit is set, When the SERR# Enable bit in the PCR registeris set and the bridge detects the assertion of S_SERR# on the Secondary bus, it will then assertP_SERR# on the Primary interface. When clear, S_SERR# assertions are not forwarded to the Primaryinterface.00 0 2Secondary interface. When this bit is clear, all address and data parity errors on the Secondary interfacewill be ignored. When this bit is set, detection and reporting of all parity errors on the SecondarySecondary Parity Error Response Enable - This bit controls the response to parity errors on theinterface is enabled. Correct parity must be generated even when parity error reporting is disabled.4-108 Developer’s Manual