Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitFigure 4-10.64-Bit Write Request with 32-Bit TransferCLK1 2 3 4 5 6 7 8 9FRAME#REQ64#AD[31:00]ADDRDATA-1DATA-2DATA-3AD[63:32]DATA-2C/BE[3:0]#BUS CMD BE#s-1 BE#s-2 BE#s-3C/BE[7:4]#BE#s-2IRDY#TRDY#DATA TRANSFERDATA TRANSFERWAITWAITWAITDATA TRANSFERDEVSEL#ACK64#ADDRESSPHASEDATAPHASEDATAPHASEDATAPHASEAs a PCI-to-PCI bridge, the Intel ® 80312 I/O companion chip may be in a system environmentwith 64-bit devices on one bridge side and 32-bit devices on the other bridge side. This createspotential problems when a 64-bit master performs a delayed read to a 32-bit target, with aprefetching PCI Local Bus Specification, Revision 2.2 bridge in the data path withinnon-prefetching address space. To account for this, the following rules apply to bridge readbehavior:• For a non-prefetchable read, the bridge will never return ACK64# and will always perform a32-bit read (REQ64# not asserted) on the target interface.• As is the case in all delayed reads, a disconnect during the delayed completion cycle on thetarget bus does not result in any additional reads.• For all prefetchable reads, when the initiator starts a transaction with A2=0, the target interfacewill assert REQ64#. When the initiator starts a transaction with A2=1, the target interface willnot assert REQ64#. This means that a 32-bit requestor can transfer data from a 64-bit target ona 64-bit target bus. When the read completion data is completely buffered and QWORDaligned at the tail end, the bridge will return the data as a 64-bit target.• Delayed reads in prefetchable address space can return 64-bit data to a 64-bit master on theinitiating bus even when the read on the target bus was from a 32-bit target.• REQ64# is required to be asserted on a Retry sequence by the master but the target is under noobligationtoassertACK64# during the completion cycle even when it was asserted during theoriginal transaction when the delayed read was enqueued and initiated.Developer’s Manual 4-35