Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipGeneral Purpose Input Output (GPIO)13.2 Register DefinitionsAll three GPIO registers are visible as Intel ® 80200 processor memory mapped registers and canbe accessed through the internal memory bus. Each is a 8-bit register and is memory-mapped in theIntel ® 80200 processor memory space. The memory-mapped addresses of the GPIO controlregisters are found in Appendix A, “Peripheral Memory-Mapped Registers.”There are three registers for the General Purpose Input/Output pins:• GPIO Output Enable Register• GPIO Input Data Register• GPIO Output Data Register13.2.1 GPIO Output Enable Register - GPOEThe GPIO Output Enable Register enables on a per pin basis the output value contained in theGPIO Output Data Register onto the appropriate pin.The GPIO Output Enable Register is initialized to the value of the eight associated GPIO pins uponassertion of P_RST#. The I/O pin design provides internal weak pull-up devices that are driven onthe GPIO pin during P_RST# assertion.In order to enable a particular GPIO pin to operate as an output following the deassertion ofP_RST#, the user needs to provide a weak pull-down on the GPIO pin, to overdrive the internalweak pull-up device.Table 13-1. GPIO Output Enable Register - GPOE (Sheet 1 of 2)IOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesnanananananananaIntel ® 80200 Processor Local Bus Address0000 171CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description0706GPIO[7]duringP_RST#assertionGPIO[6]duringP_RST#assertionGPIO7 Output Enable -- When clear, bit 7 of GPIO Output Data Register is enabled onto GPIO[7] pin.GPIO6 Output Enable -- When clear, bit 6 of GPIO Output Data Register is enabled onto GPIO[6] pin.13-2 Developer’s Manual