Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.2.3 Direct Addressing WindowThe second method used by outbound cycles from the Intel ® 80312 I/O companion chip to the PCIbus is the direct addressing window. This is a window of addresses in Intel ® 80312 I/O companionchip address space that act in the same manner as the outbound translation windows either withoutany translation or with the translation of address bit 31 only. This allows the Direct Addressingwindow to translate to different address ranges on the PCI bus (0000.2000H to 7FFF.FFFFH or8000.2000H to FFFF.FFFFH). A Intel ® 80312 I/O companion chip read or write to a local busaddress within the direct addressing window initiates a read or write on the PCI bus with the sameaddress (with the possible exception of address bit 31) as used on the internal bus. Figure 5-7shows two examples of outbound writes that are through the direct addressing window.Direct Addressing is limited to PCI memory read commands and writes only. I/O cycles, DACcycles, and MWI commands are not supported with direct addressing.Figure 5-7.Direct Addressing WindowIntel ® 80312 I/O Companion Chip Local Address SpaceUpper 2 GbyteTranslation Disabled 0000 2000HInternal Bus Writewith address6000 1008HUpper 2 GbyteTranslation EnabledInternal Bus Writewith address 6000 1008HDirect Addressing WindowNo Address Translation7FFF FFFFH0000 2000HDirect Addressing WindowAddress Translation7FFF FFFFHPCI Write Cyclewith address6000 1008HPCI Write Cyclewith address E000 1008HThe internal bus side of the direct addressing window address range is fixed in the lower 2 Gbytesof the Intel ® 80312 I/O companion chip local address space (except for the first 8 Kbytes which isreserved for the Intel ® 80200 processor internal data RAM and Intel ® 80312 I/O companion chipmemory-mapped registers). Internal bus cycles with an address from 0000.2000H to 7FFF.FFFCHare forwarded to a PCI bus, when enabled. The primary PCI bus is the default bus for directaddressing. The following bits within the ATUCR affect direct addressing operation:• ATUCR Direct Addressing Enable bit - when set, enables the direct addressing window. Whenclear, addresses within the direct addressing window are not forwarded to the PCI bus.• ATUCR Secondary Direct Addressing Select bit - when clear, all transactions through thedirect addressing window are to the primary ATU and primary PCI bus. When set, alltransactions through the direct addressing window are to the secondary ATU and secondaryPCI bus.• ATUCR Direct Addressing Upper 2G Translation Enable - when set, the ATU forwardsinternal bus cycles with an address between 0000.2000H and 7FFF.FFFFH to the PCI bus withbit 31 of the address set (8000.2000H - FFFF.FFFFH). When clear, no translation occurs.Developer’s Manual 5-19