Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitWhen a data parity error is detected on the target bus by the target of a posted write transactionwhen the bridge did not detect a data parity error on the initiating bus, the master of the transactionhas no way of knowing that the data parity error has occurred (since PERR# cannot be forwardedback to the master due to the two clock cycle restriction for PERR# and data transferred).P_SERR# is used to notify the Primary interface of an error of this type. P_SERR# is only usedwhen the data parity error occurs on the target bus and was not detected on the initiating bus.For a downstream transaction, where no data parity error was detected on the Primary interface,which is completing on the Secondary bus and S_PERR# is detected by the Secondary interfacethe following actions are performed with the given constraints:• The Data Parity Detected bit in the SSR is set when the Secondary Parity Error Enable bit isset in the BCR. When the Data Parity Detected bit is set in the SSR and the Secondary PCIMaster Parity Error Interrupt Mask bit is clear in the SDER, set the Data Parity Detected bit inthe SBISR.• P_SERR# is asserted when:— the Secondary Parity Error Enable bit is set in the BCR— the Primary Parity Error Enable bit is set in the PCR—theSERR# Enable bit is set in the PCRFor an upstream transaction, where no data parity error was detected on the Secondary interface,whichiscompletingonthePrimarybusandP_PERR# is detected by the Primary interface thefollowing actions are performed with the given constraints:• The Data Parity Detected bit in the PSR is set when the Primary Parity Error Enable bit is setin the PCR. When the Data Parity Detected bit is set in the PSR and the Primary PCI MasterParity Error Interrupt Mask bit is clear in the SDER, set the Data Parity Detected bit in thePBISR.• P_SERR# is asserted when:— the Secondary Parity Error Enable bit is set in the BCR— the Primary Parity Error Enable bit is set in the PCR—theSERR# Enable bit is set in the PCR4.11.3 SERR# AssertionWhenever S_SERR# is asserted on the Secondary interface of the bridge, the bridge must assertP_SERR# on the Primary interface when the following is true:• The SERR# Enable bit is set in the PCR.• The Secondary SERR# Enable bit is set in the BCRThe bridge must also set the Received System Error bit in the SSR. This function propagates theerror upstream to the Primary interface. When the Received System Error bit in the SSR is set andthe S_SERR# Detected Interrupt Mask bit in the SDER is clear, the S_SERR# Detected bit is setin the SBISR.4-72 Developer’s Manual