Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMemory Controller3.6.13 Flash Bank Size Register 1 - FBSR1These registers indicate the size of Flash bank 1. The two Flash banks do not have to be equal insize. When the bank is unpopulated, a value of zero is programmed. See Section 3.2.2.1, “FlashMemory Addressing” on page 3-7 for more details.Table 3-30.Flash Bank Size Register 1 - FBSR1IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address1558HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:04 0 Reserved03:00 1000Flash Bank Size: Defines the size for the Flash bank.• 0000 - Bank disabled• 0001 - 64 Kbytes• 0010 - 128 Kbytes• 0011 - 256 Kbytes• 0100 - 512 Kbytes• 0101 - 1 Mbytes• 0110 - 2 Mbytes• 0111 - 4 Mbytes• 1XXX - 8 Mbytes3-58 Developer’s Manual
Intel ® 80312 I/O Companion ChipMemory Controller3.6.14 Flash Wait States Registers - FWSR0, FWSR1These registers indicate the wait state and recovery cycle profile of each physical Flash bank.Programmability for up to 20 address-to-data wait states is included to accommodate UARTdevices. For more details, see Section 3.2.2.2, “Flash Read Cycle” on page 3-8 and Section 3.2.2.3,“Flash Write Cycle” on page 3-10.Table 3-31.Flash Wait State Registers - FWSR0, FWSR1IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rv rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaBank #01Intel ® 80200 Processor Local Bus Address155CH1560HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not Accessible06:04 111 202:00 111 2Bit Default Description31:07 0 Reserved• 010 - 8 Recovery wait statesRecovery Cycle Wait States: Defines the number of recovery cycle wait states for the Flash bank.• 000 - 1 Recovery wait state• 001 - 4 Recovery wait states• 011 - 12 Recovery wait states• 100 - 16 Recovery wait states• Others (Default) - 20 Recovery wait states03 0 2 Reserved• 001 - 8 Address-to-Data wait statesAddress-to-Data Wait States: Defines the number of address-to-data wait states for the Flashbank during a read or write transaction.• 000 - 4 Address-to-Data wait states• 010 - 12 Address-to-Data wait states• 011 - 16 Address-to-Data wait states• Others (Default) - 20 Address-to-Data wait statesDeveloper’s Manual 3-59
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Memory Controller 3This chapter des
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Intel 80312 I/O Companion Chip - ECEE

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