Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.3.5 Appending to The End of a ChainOnce a channel has started processing a chain of DMA descriptors, the application software mayneed to append a chain descriptor to the current chain without interrupting the transfer in progress.The mechanism used for performing this action is controlled by the Chain Resume bit in theChannel Control Register.The channel reads the subsequent chain descriptor each time the channel completes the currentchain descriptor and the Next Descriptor Address Register is non-zero. The Next DescriptorAddress Register always contains the address of the next chain descriptor to be read and theDescriptor Address Register always contains the address of the current chain descriptor.The procedure for appending chains requires the software to find the last chain descriptor in thecurrent chain and change the Next Descriptor Address in that descriptor to the address of the newchain to be appended. The software then sets the Chain Resume bit in the Channel Control Registerfor the channel. It does not matter when the channel is active or not.The channel examines the Chain Resume bit of the CCR when the channel is idle or uponcompletion of a chain of DMA transfers. When this bit is set, the channel re-reads the NextDescriptor Address of the current chain descriptor and load it into the Next Descriptor AddressRegister. The address of the current chain descriptor is contained in the Descriptor AddressRegister. The channel clears the Chain Resume bit and then examine the Next Descriptor AddressRegister. When the Next Descriptor Address Register is not zero, the channel reads the chaindescriptor using this new address and begin a new DMA transfer. When the Next DescriptorAddress Register is zero, the channel remains or return to idle.There are three cases to consider:1. The channel completes a DMA transfer and it is not the last descriptor in the chain. In thiscase, the channel clears the Chain Resume bit and reads the next chain descriptor. Theappended descriptor is read when the channel reaches the end of the original chain.2. The channel completes a DMA transfer and it is the last descriptor in the chain. In this case,the channel examines the state of the Chain Resume bit. When the bit is set, the channelre-reads the current descriptor to get the address of the appended chain descriptor. When thebit is clear, the channel returns to idle.3. The channel is idle. In this case, the channel examines the state of the Chain Resume bit whenthe CCR is written. When the bit is set, the channel re-reads the last descriptor from themost-recent chain to get the appended chain descriptor.9-12 Developer’s Manual