Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.5.1.2 Inbound Read Queues and Inbound Transaction QueuesThe inbound read queues are responsible for retrieving data from local memory and returning it tothe PCI busses in response to a delayed read transaction initiated from a PCI master. The ATUseach have one IRQ for data only. The address of the transaction is held in a dedicated ITQ. P_ITQ1and P_ITQ2 are dedicated to P_IRQ with a similar arrangement for the secondary ATU queues.Each IRQ holds the data from only one read transaction from the PCI bus. The read request cycleon PCI latches the read command and the address into the ITQ when the cycle is first initiated bythe PCI master. The ATU IB master interface takes the translated address and the command andperforms a read on the internal bus. Reads can be any of the PCI memory read command typesusing the ATU inbound translation or an inbound configuration read using the specificconfiguration cycle translation. The data from the read on the IB is stored in the IRQ until the PCImaster initiates a read cycle that matches the initial request cycle in both command and address.Any data left in an IRQ after the delivery of a completion cycle on PCI is flushed. This is possiblesince all internal bus memory is considered prefetchable with no read side effects.The exact amount of data read by the master state machine on the IB interface depends upon theread command used and how much data the PCI target device delivers. Table 5-5 shows the amountof data attempted to be read for the different memory read commands for both the primary andsecondary ATUs. In addition, memory read streaming is used. This means that when an IRQ iscurrently being drained while it is being filled and the prefetch size is reached, the ATU internalbus master maintains the transaction and continues filling read data into the IRQ until it fills up. Ifthe IRQ reaches a full state while being drained, the ATU internal bus master relinquishes the bus.No master wait states are inserted. If additional read prefetch data is entered into the queue after thedraining master gives up the PCI bus, the data is flushed.The function of the two transaction queues for each data queue is to allow the acceptance of up totwo delayed read requests. While only 1 read completion can be occurring at any one time, thesecond DRR can be accepted to reduce the latency of accepting another DRR after the previousDRC has completed. For example, a DRR can be accepted into P_ITQ1. After the DRR has beenaccepted and the read starts on the internal bus, data starts filling P_IRQ from the internal bus side.While this is occurring the PCI slave interface is capable of accepting another independent readrequest into P_ITQ2. This read only begins on the internal bus after a PCI master has performed aread completion cycle on PCI and has drained the read data associated with P_ITQ1 from P_IRQ.Under no circumstances does the read data queue hold read data from more than one transactionqueue at a time.Internal bus error conditions override all prefetch amounts. i.e. a master-abort and target-abortconditions.Table 5-5.Inbound Read Prefetch Data SizesATU PCI Read Command Prefetch Size (Bytes)Memory Read 32PATUSATUMemory Read Line 128Memory Read Multiple 256Memory Read 32Memory Read Line 128Memory Read Multiple 2565-34 Developer’s Manual