13.07.2015 Views

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

SHOW MORE
SHOW LESS
  • No tags were found...

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Memory ControllerThe base register defines the upper seven address bits of the SDRAM memory space. Theboundary registers define the address limits for each SDRAM bank in 32 Mbyte granularity.Table 3-8 defines the conditions which must be satisfied to activate an SDRAM memory bank.Table 3-8.Address Decoding for SDRAM Memory SpaceConditionI_AD[31:29] is not equal to the SDBR[31:29]I_AD[31:25] is greater than or equal to the SDBR[31:25]I_AD[28:25] is less than the value in SBR0[7:3]I_AD[31:25] is greater than or equal to the SDBR[31:25]I_AD[28:25] is greater than or equal to the value in SBR0[7:3]I_AD[28:25] is less than the value in SBR1[7:3]Example 3-1. Address Register Programming Example 1NoneBank 0Bank 1SDRAM Bank SelectedThe user wants to program the SDRAM memory space to begin at A000 0000H. Bank 0 is 32Mbytes and Bank 1 is 64 Mbytes yielding in a total memory of 96 Mbytes. The registers would beprogrammed as follows:SDBR = A000 0000HSBR0[7:3] = 00001 2 = 01HSBR1[7:3] = 00011 2 = 03HExample 3-2. Address Register Programming Example 2The user wants to program the SDRAM memory space to begin at A000 0000H. Bank 0 is 32Mbytes and Bank 1 is unpopulated. The registers would be programmed as follows:SDBR = A000 0000HSBR0[7:3] = 00001 2 = 01HSBR1[7:3] = 00001 2 = 01HExample 3-3. Address Register Programming Example 3The user wants to program the SDRAM memory space to begin at A000 0000H. Bank 0 is 32Mbytes and Bank 1 is 32 Mbytes yielding in a total memory of 64 Mbytes. The registers would beprogrammed as follows:SDBR = A000 0000HSBR0[7:3] = 00001 2 = 01HSBR1[7:3] = 00010 2 = 02HTable 3-9 shows the programming for SDRAM memory spaceTable 3-9.Programming Values for the SDRAM Boundary Registers (SBRx[7:3])Bank Size Bank 0 (SBR0) Bank 1 (SBR1)Empty SBR0 = 0x00 + SDBR[28:25] SBR1 = 0x00 + SBR0[7:3]32M SBR0 = 0x01 + SDBR[28:25] SBR1 = 0x01 + SBR0[7:3]64M SBR0 = 0x02 + SDBR[28:25] SBR1 = 0x02 + SBR0[7:3]128M SBR0 = 0x04 + SDBR[28:25] SBR1 = 0x04 + SBR0[7:3]256M SBR0 = 0x08 + SDBR[28:25] SBR1 = 0x08 + SBR0[7:3]3-14 Developer’s Manual

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!