Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.3.1 Secondary PCI Bus Arbitration UnitAfter reset, all devices controlled by the secondary PCI Bus Arbiter are set to low priority, exceptfor the secondary PCI interface of the Intel ® 80200 processor, which is set to high priority.The secondary bus arbiter is reset by the S_RST# signal on the secondary interface. Whenever thesecondary bus is reset, the secondary arbiter is reset moving all devices to their programmedpriority levels and starting the round robin arbitration sequence on the lowest number device ateach priority level.15.3.2 Internal Bus Arbitration UnitThe internal bus arbitration logic is reset by the P_RST# signal. The reset values of the registersare shown in Table 15-7. All bus masters are initialized to the highest priority. None of the devicesare disabled at powerup.Table 15-7.Reset ValuesInternal Arbitration Register Reset Value NoteInternal Arbitration Control Register (IACR) 0000 0000H All Bus Masters EnabledMaster Latency Timer Register (MLTR) 0000 0FFFH Maximum Count ValueMulti-Transaction Timer Register (MTTR) 0000 0000H Disabled15.3.3 Reset State OperationThe P_RST# signal, when asserted, causes the Intel ® 80312 I/O companion chip to enter the resetstate. All external signals go to a defined state, internal logic is initialized, and certain registers areset to defined values.P_RST# must be asserted when power is applied to the processor. The processor then stabilizes inthe reset state. This power-up reset is referred to as cold reset. To ensure that all internal logic hasstabilized in the reset state, a valid input clock (S_CLK) andV CC must be present and stable for aspecified time before P_RST# can be deasserted.The processor may also be cycled through the reset state after execution has started. This is referredto as warm reset. For a warm reset, P_RST# must be asserted for a minimum number of clockcycles.15-14 Developer’s Manual