Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.2 Theory of OperationThe PMON facility provided on the Intel ® 80312 I/O companion chip comprises:• One dedicated Global Time Stamp counter, and• Fourteen (14) programmable event counters.The global time stamp counter is a dedicated, free running 32-bit counter clocked at one quarter theinternal bus frequency. It provides a time base for monitoring all events on the Intel ® 80312 I/Ocompanion chip. Event counters are used to monitor events across different interfaces of theprocessor.11.2.1 Global Time StampThe Global Time Stamp Counter is a dedicated, 32-bit counter provided on-chip. It contains adivisor which provides the input clock to the global time stamp counter. The counter is clocked atone quarter the internal bus frequency. The counter is cleared upon the deassertion of the InternalBus Reset signal. The counter interrupts the Intel ® 80200 processor based on Intel ® XScale microarchitecture (ARM* architecture compliant) when the interrupt bit (bit 0) in the Global TimerMode Register (GTMR) is set. With the bit set, the counter sets bit 0 in the Event MonitoringInterrupt Status Register (EMISR) when it overflows. When this bit is set, an interrupt is generatedto the Intel ® 80200 processor on the FIQ1# interrupt pin. An overflow condition is defined as acounter rolling over from FFFF FFFFH to 0000 0000H.Once the counter reaches the maximum value, it rolls over to zero and increments at the clockfrequency. The value in the counter is accessible at all times by reading the memory mapped,Global Time Stamp Register (GTSR). The GTSR is a read-only register.11.2.2 Programmable Event CountersThere are fourteen (14) general-purpose, 32-bit wide Programmable Event Counters (PECx). Eachcounter is programmed to monitor an event from a predetermined list of events. Depending on themonitored interface, the event tracked in any counter varies. Each counter is accessible through amemory-mapped, read-only register.The programmable event counters provide real-time monitoring capability. The current count valuecontained in any counter is obtained by accessing the corresponding memory-mapped register.Any counter that overflows sets the corresponding bit in the Event Monitoring Interrupt StatusRegister (EMISR). Once a counter reaches the maximum value, it rolls over to zero and startsincrementing. For example, when PEC1 overflows, it sets bit1 in the EMISR. Similarly, when anyother counter (PEC2 - PEC14) overflows, the corresponding bit in the EMISR (bit2:14) is set.Once a bit in the EMISR is set, an interrupt is generated to the Intel ® 80200 processor on theFIQ1# interrupt pin.All event counters and the Global Time Stamp Counter are disabled after RESET and the valuescontained are undefined. All counters including the Global Time Stamp Counter are initialized tozero when a specific monitoring mode is chosen by writing a value to the Event Select Register(ESR) during performance monitoring. The fourteen programmable event counters monitor bothkinds of events: occurrence events and duration events.11-2 Developer’s Manual
Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.2.2.1 Occurrence EventsAn occurrence event is counted each time the event occurs. Table 11-1 lists the various occurrenceevents that are monitored on the Intel ® 80312 I/O companion chip.Table 11-1.Occurrence EventsObserved InterfaceMonitored EventNumber of grants to the BridgeNumber of grants to Secondary Address Translation UnitSecondary PCI busPrimary PCI busIntel ® 80312 I/Ocompanion chip internalbusNumber of grants to DMA Ch-2Number of grants to the Intel ® 80312 I/O companion chipNumber of grants to external PCI masters 0..5Number of grants to the BridgeNumber of grants to Primary Address Translation Unit (PATU)Number of grants to DMA Ch-0 and Ch-1Number of grants to Intel ® 80200 processor.Number of grants to DMA Ch-0, Ch-1 and Ch-2Number of grants to Application AcceleratorNumber of times backoff (BOFF) asserted by Primary Address Translation Unit(PATU)Number of times backoff (BOFF) asserted by Secondary Address Translation Unit(SATU)Number of grants to PATU and SATUDeveloper’s Manual 11-3
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Intel 80312 I/O Companion Chip - ECEE

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