Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipDMA Controller Unit9.3.4 Synchronizing a Program to Chained TransfersChained DMA transfers can be synchronized to a program executing on the Intel ® 80200 processorthrough the use of processor interrupts. The channel generates an interrupt to the Intel ® 80200processor under certain conditions. They are:1. [Interrupt & Continue] The channel completes the data transfer for a chain descriptor and theNext Descriptor Address Register is non-zero. When the Interrupt Enable bit within theDescriptor Control Register is set, an interrupt is generated to the Intel ® 80200 processor. Thisinterrupt is for synchronization purposes only. The channel sets the End Of Transfer Interruptflag in the Channel Status Register. Since it is not the last chain descriptor in the list, the DMAchannel starts to process the next chain descriptor without requiring any processor interaction.2. [End of Chain] The DMA channel completes the data transfer for a DMA chain descriptor andthe Next Descriptor Address Register is zero specifying the end of the chain. When theInterrupt Enable bit within the Descriptor Control Register is set, an interrupt is generated tothe Intel ® 80200 processor. The channel sets the End Of Chain Interrupt flag in the ChannelStatus Register.3. [Error] An error condition occurs (refer to Section 9.12 for DMA error conditions) during aDMA transfer. The channel halts operation on the current chain descriptor and not proceed tothe next chain descriptor.Each chain descriptor can independently set the Interrupt Enable bit in the Descriptor Controlword. This bit enables an independent channel interrupt upon completion of the data transfer forthe chain descriptor. This bit can be set or clear within each chain descriptor. Control of interruptgeneration within each descriptor aids in synchronization of the executing software with DMAtransfers.Figure 9-6 shows two examples of program synchronization. The left column shows programsynchronization based on individual chain descriptors. Descriptor 1A generated an interrupt to theprocessor, while descriptor 2A did not because the Interrupt Enable bit was clear. The lastdescriptor nA, generated an interrupt to signify the end of the chain has been reached. The rightcolumn in Figure 9-6 shows an example where the interrupt was generated only on the lastdescriptor signifying the end of chain.9-10 Developer’s Manual
Intel ® 80312 I/O Companion ChipDMA Controller UnitFigure 9-6.Synchronizing to Chained TransfersIndependent Interrupt after Completing any Descriptorchain descriptorsInterrupt after Completing Last Descriptorchain descriptorsDescriptor 1AOptional interruptgenerated tointerrupt procedureRET.Descriptor 1BDescriptor 2ADescriptor 2B.No Interrupt on this DescriptorDescriptor nB.Descriptor nAinterrupt procedureRET.interrupt procedureRET.Developer’s Manual 9-11
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Intel 80312 I/O Companion Chip - ECEE

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