Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.3.4 The Bitwise-XOR AlgorithmFigure 10-7 describes the XOR algorithm implementation. In this illustrative example, there arefour blocks of source data to be XOR-ed. The intermediate result is kept by the store queue in theAAU before being written back to Intel ® 80200 processor local memory. The source data is locatedat addresses A000 0400H, A000 0800H, A000 0C00H and A000 1000H respectively.All data transfers needed for this operation are controlled by chain descriptors located in localmemory. The Application Accelerator as a master on the internal bus initiates data transfer. Thealgorithm is implemented such that as data is read from local memory, the boolean unit executesthe XOR operation on incoming data.Figure 10-7.The Bit-wise XOR AlgorithmIntel ® 80200 processor Local MemoryMSBLSBBlock 1A000 0400H1024 bytesbytes 1-8bitwise-XOR(64-bit wide)Block 21024 bytesbytes 1-8A000 0800Hbitwise-XOR(64-bit wide)Block 31024 bytesbytes 1-8A000 0C00Hbitwise-XOR(64-bit wide)Block 41024 bytesbytes 1-8A000 1000Hbyte 8byte 1... ... ...B000 0400H1K byte128-DeepStore QueueControl Register ValuesSAR1 = A000 0400HSAR2 = A000 0800HSAR3 = A000 0C00HSAR4 = A000 1000HDAR = B000 0400HABCR = 0000 0400HADCR = 8000 049FH10-10 Developer’s Manual
Intel ® 80312 I/O Companion ChipApplication Accelerator UnitFigure 10-8.Hardware Assist XOR UnitNew DataXOReddata Each existing bit is XORed with new dataand stored back to the same bit location...bytes 1 - 8bytes 9-16Byte 1 = Byte 1 ⊕ Byte 1 ⊕ Byte 1 ⊕ Byte 1Block 1Block 2 Block 3 Block 4bytes 1021-1024Byte 1024 = Byte 1024 ⊕ Byte 1024 ⊕ Byte 1024 ⊕ Byte 1024Block 1 Block 2 Block 3 Block 4Developer’s Manual 10-11
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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Intel 80312 I/O Companion Chip - ECEE

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