Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.2 Theory of OperationThe CIU allows the Intel ® 80200 processor to access flash memory, local memory (PC-100SDRAM), internal Intel ® 80312 I/O companion chip functional units such as the AAU andAddress Translation Units (ATUs), internal functional unit MMRs and external PCI clients on theprimary PCI and secondary PCI buses connected to the Intel ® 80312 I/O companion chip.The CIU supports four types of memory access by the Intel ® 80200 processor:1. Data transfers from the Intel ® 80200 processor to the Intel ® 80312 I/O companion chipinternal bus agents (other than memory controller) require the MCU is not currently granteddata bus ownership. The Intel ® 80200 processor arbitrates for data bus ownership, issues awrite request to the CIU and data to the data bus. The CIU queues and translates the commandand data, and executes write commands as PCI bus master required to transfer the data to theappropriate internal bus agent.2. Data Transfers from the Intel ® 80200 processor to the MCU controlled SDRAM aremulti-stage accesses. The Intel ® 80200 processor arbitrates for data bus ownership, issues awrite request to the CIU and data to the data bus. The CIU queues and translates the commandand data, and executes write commands as PCI bus master required to transfer the data to theMCU via the internal bus. The MCU writes the data to SDRAM.3. When transferring data to the Intel ® 80200 processor from the Intel ® 80312 I/O companionchip internal bus agents (other than the memory controller) the Intel ® 80200 processor issues aread request to the CIU. The CIU queues and translates the command, and executes readcommands as PCI bus master required to transfer the data from the appropriate internal busagent. Prior to requesting ownership of the internal bus, the CIU asserts hold_mcu and waitsfor hold_mcu_ack to signal that the MCU allows the CIU to drive the SDRAM bus. Data fromthe internal bus is transferred to the Intel ® 80200 processor via the SDRAM data bus.4. Data Transfers to the Intel ® 80200 processor from the MCU controlled SDRAM aremulti-stage. The Intel ® 80200 processor issues a read request to the CIU. The CIU queues andtranslates the command, obtains exclusive ownership of the MCU, executes read commands asPCI bus master required to transfer the data from the target MCU. The MCU fetches data fromSDRAM for transfer to the CIU (PCI delayed reads not used). The Intel ® 80200 processorregisters data directly off of the data bus under CIU control. The CIU must then “discard” theredundant data transferred on the internal bus by the MCU by performing protocol correct,properly terminated phantom PCI cycles. Errors are not detected or corrected by the MCU, forthe Intel ® 80200 processor loads, since those calculations are performed inside the Intel ®80200 processor. Corrupted data fetched from SDRAM by the MCU is forwarded to the CIUvia the internal bus, as if good data was fetched from SDRAM (without target aborting thetransfer).The CIU allows the Intel ® 80200 processor to access the Intel ® 80312 I/O companion chipcontrolled local memory (PC-100 SDRAM), access the Intel ® 80312 I/O companion chipMMRs for Intel ® 80312 I/O companion chip configuration, status updates and error handling,access PCI host bus clients via the Intel ® 80312 I/O companion chip primary ATU and accessPCI storage and I/O clients via the Intel ® 80312 I/O companion chip secondary ATU. TheSDRAM data and check bit buses also serve multiple functions - normal SDRAM loads andstores are interleaved with the Intel ® 80200 processorstore data presentation and the Intel ®80200 processor internal bus load data fetches from the internal bus.The Intel ® 80200processor load data fetches obtained from SDRAM are transferred directly from SDRAM tothe Intel ® 80200 processor, requiring the Intel ® 80200 processor internal ECC logic to be usedfor error detection and correction.TheCIUmayaddressanytargetontheIB.8-2 Developer’s Manual