Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.7.3 FIQ2 Interrupt Status Register- FIQ2ISRThe FIQ2 Interrupt Status Register (FIQ2ISR) contains the current pending FIQ2 interrupts. Thesource of the FIQ2 interrupt can be the internal peripheral devices connected through the FIQ2Interrupt Latch. The interrupts which can be generated on the FIQ1# input are detailed inSection 2.4.3, Intel ® 80312 I/O Companion Chip: Internal Peripheral Interrupt Routing.The FIQ2ISR is used by application software to determine the source of an interrupt on the FIQ1#input and to clear that interrupt. All bits within this register are defined as read only. The bits withinthis register are cleared when the source of the interrupt (status register source shown in Table 2-4)are cleared. The FIQ2ISR reflects the current state of the input to the FIQ2 Interrupt Latch.Due to the asynchronous nature of the Intel ® 80312 I/O companion chip peripheral units, multipleinterrupts can be active when application software reads the FIQ2ISR register. Applicationsoftware must handle these multiple interrupt conditions appropriately. In addition, applicationsoftware may subsequently read the FIQ2ISR register to determine when additional interrupts haveoccurred during interrupt processing for the prior interrupts.Table 2-10 details the bit definition of the FIQ2ISR.Table 2-10.FIQ2 Interrupt Status Register- FIQ2ISRIOPAttributesPCIAttributes31 28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro ro rvinisdbqcna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 Processor Local BusAddress0000 1704HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA= Not AccessibleBit Default Description31:03 0 Reserved02 0 2Messaging Unit Interrupt Pending - when set, an interrupt from the Messaging Unit is pending. When clear,no interrupt is pending.01 0 2I 2 C Interrupt Pending - when set, an interrupt is from the I 2 C Bus Interface Unit is pending. When clear, nointerrupt is pending.00 0 2 Reserved2-14 Developer’s Manual