Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitFigure 4-1 shows a block diagram of the Intel ® 80312 I/O companion chip PCI-to-PCI Bridge unit.Figure 4-1.PCI-to-PCI Bridge Unit Functional Block DiagramInternal Bus(for Configuration Only)PCI-to-PCI BridgeConfiguration Registers256 Byte Address SpaceD_PMWDU_DRC0U_DRC1U_DRC2D_DWCDownstream Posted Memory Write (PMW) 128 Bytes DataUpstream Delayed Read Completion (DRC) 256 Bytes DataUpstream Delayed Read Completion (DRC) 256 Bytes DataUpstream DRC; 4 Bytes DataDownstream DRC; 4 Bytes DataD_PMWADDownstream PMWAddress Queue(4 Entries)D_TRQ0:2Downstream DRRTransaction Queues(3)U_TRQ3Up. DWR Trans: Q (1)Primary PCI66 MHz / 64-BitUpstream Posted Memory Write (PMW) 256 Bytes DataDownstream DRC 64 Bytes DataDownstream DRC 64 Bytes DataD_PMWDU_DRC0U_DRC1Secondary PCI66 MHz / 64-BitU_TRQ0:2Upstream DRRTransaction Queues(3)U_PMWADUpstream PMWAddress Queue(8 Entries)Downstream DRC; 4 Bytes DataUpstream DRC; 4 Bytes DataU_DRC2D_DWCD_TRQ3Downstr. DWR Trans: Q (1)A8298-014-2 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.2 Theory of OperationThe bridge unit operates as an address filter unit between the Primary and the Secondary PCIbuses. PCI supports three separate address spaces:• 32-Bit address space with Single Address Cycle (SAC)• 64-Bit address space with Dual Address Cycle (DAC)• 64 Kbyte I/O address space (with 16-bit addressing)• Separate configuration spaceA PCI-to-PCI bridge is programmed with a contiguous range of addresses within the memory andI/O address spaces, which then become the Secondary PCI address space. Any address present onthe Primary side of the bridge which falls within the programmed Secondary space is forwardedfrom the Primary to the Secondary side while addresses outside the Secondary space are ignored bythe Primary interface. The Secondary side of the bridge works in reverse of the Primary side,ignoring any addresses within the programmed Secondary address space and forwarding anyaddresses outside the Secondary space to the Primary side. See Figure 4-2.The Primary and Secondary interfaces of the PCI bridge each implement PCI PCI-to-PCI BridgeArchitecture Specification, Revision 1.1 compliant master and target devices. A PCI transactioninitiated on one side of the bridge will address the initiating bus bridge interface as a target and thetransaction will be completed by the target bus interface operating as a master device. The bridge issoftware transparent to PCI devices on either side.Figure 4-2.Bridge OperationPrimary PCI Address Space0000.0000HSecondary PCI Address Space0000.0000HTransactionsForwarded Upstream toThe Primary PCI BusValid PrimaryPCI AddressesValidSecondary PCIAddressesTransactions ForwardedDownstream to TheSecondary PCI BusValidSecondary PCIAddressesFFFF.FFFFH64-Bit DACAddressesTransactions ForwardedUpstream to The PrimaryPCI BusFFFF.FFFFHAll TransactionsForwarded Upstream toThe Primary PCI BusValid PrimaryPCIAddresses64-Bit DACAddressesSecondary PCIAddress remainon the SecondaryPCI Bus and areNever ForwardedUpstreamFFFF.FFFF.FFFF.FFFFHFFFF.FFFF.FFFF.FFFFHThe PCI-to-PCI bridge unit of the Intel ® 80312 I/O companion chip adheres, at a minimum, to therequired features found in the PCI-to-PCI Bridge Architecture Specification, Revision 1.1 and thePCI Local Bus Specification, Revision 2.2. This chapter will describe bridge functionality and willrefer to the PCI-to-PCI Bridge Architecture Specification, Revision 1.1 and the PCI Local BusSpecification, Revision 2.2 where appropriate.Developer’s Manual 4-3
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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DMA Controller Unit 9This chapter d
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