Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.18 Memory Limit Register - MLRMemory Limit Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2. The Memory Limit Register defines the upper address (inclusive) of thememory-mapped I/O address range (non-prefetchable) that is used to determine when to forwardmemory transactions from one side of the bridge to the other. The Memory Limit Register must beprogrammed to a value greater than or equal to the MBR before the Memory Space Enable bit ofthe Primary Command Register is set. The upper 12 bits correspond to AD[31:20] of 32-bitaddresses. For the purposes of address decoding, the bridge assumes that AD[19:0], thelower20 bits of the memory limit address, are FFFFFH. This forces a 1 Mbyte granularity on thememory address range.The VGA Enable bit in the BCR register forces the bridge to forward memory accesses in theaddress range from 0A0000H to 0BFFFFH from the Primary to Secondary and blocks addresses inthe same range from Secondary to Primary.Table 4-41.Memory Limit Register - MLRIOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rwrw rw rwrvrvrvrvPCI Configuration Offset22 - 23HIntel ® 80200 Processor Local Bus Address0000 1022HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:04 000HMemory Limit Address - This field is programmed with AD[31:20] of the top of the memory addressrange to be passed down the hierarchy by the bridge.03:00 0H Reserved.Developer’s Manual 4-103