Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.31 Secondary Clock Disable Register - SCDRThe BDG unit provides six Secondary PCI output clocks (S_CLKOUT[5:0]). Upon assertion ofP_RST#, all of the six secondary output clocks are enabled.The Secondary Clock Disable Register provides the ability to selectively disable unused secondaryoutput clocks following deassertion of P_RST#.Table 4-52.Secondary Clock Disable Register - SCDRIOPAttributes7 4 0rv rv rw rw rw rw rw rwPCIAttributesrvrvrw rw rw rw rw rwPCI Configuration Offset56HIntel ® 80200 Processor Local Bus Address0000 1056HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:06 00 2 Reserved.Disable S_CLKOUT5 -- When set, this bit disables the operation of the S_CLKOUT5 secondary clock05 0 2 output. Instead of toggling, the output will be driven to logic 0.Disable S_CLKOUT4 -- When set, this bit disables the operation of the S_CLKOUT4 secondary clock04 0 2 output. Instead of toggling, the output will be driven to logic 0.Disable S_CLKOUT3 -- When set, this bit disables the operation of the S_CLKOUT3 secondary clock03 0 2 output. Instead of toggling, the output will be driven to logic 0.Disable S_CLKOUT2 -- When set, this bit disables the operation of the S_CLKOUT2 secondary clock02 0 2 output. Instead of toggling, the output will be driven to logic 0.Disable S_CLKOUT1 -- When set, this bit disables the operation of the S_CLKOUT1 secondary clock01 0 2 output. Instead of toggling, the output will be driven to logic 0.Disable S_CLKOUT0 -- When set, this bit disables the operation of the S_CLKOUT0 secondary clock00 0 2 output. Instead of toggling, the output will be driven to logic 0.4-118 Developer’s Manual