Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.3 I 2 C Bus OperationThe I 2 C Bus Interface Unit transfers in 1 byte increments. A data transfer on the I 2 C bus alwaysfollows the sequence:1) START2) 7-bit Slave Address3) R/W# Bit4) Acknowledge Pulse5) 8 Bits of Data6) Ack/Nack Pulse7) Repeat of Step 5 and 6 for Required Number of Bytes8) Repeated START (Repeat Step 1) or STOP12.3.1 Serial Clock Line (SCL) GenerationThe Intel ® 80312 I/O companion chip’s I 2 C unit is required to generate the I 2 C clock output whenin master mode (either receive or transmit). SCL clock generation is accomplished through the useof the ICCR value, which is programmed at initialization. The ICCR value is used in the followingequation to determine the SCL transition period:Equation 12-1. SCL Transition PeriodSCL Transition Period = ICCR Decimal Value * 80312 I/O companion chip Internal BusClock PeriodThe SCL transition period is the amount of time the clock spends in the high or low state. Whenwait states are inserted or synchronization with another master is necessary, the I 2 C unit performsthe necessary clock synchronization. The ICCR provides a simple method for determining I 2 Cclock frequencies. Table 12-4 details sample programming values for the ICCR.Table 12-4.ICCR Programming ValuesIntel ® 80312I/OCompanionChip InternalBusFrequencyICCR ValueSCLTransitionPeriodI 2 C Clock Frequency =[1/(SCL Transition Per. * 2)]100 MHz001111101 2 07DH 125 1.25 µs 400.0 KHz111110100 2 1F4H 500 5.00 µs 100.0 KHzProgramming a value less than 30H results in undefined behavior.12-8 Developer’s Manual