Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.10.2.2 DisconnectA Disconnect is used when the initiating interface is unable to respond to the initiator due to acondition like the posting buffer has become full. A Disconnect is used when data has been alreadybeen transferred to the bridge. Refer to the PCI Local Bus Specification for details on Disconnect.A Disconnect is signaled using two sequences. When STOP#, TRDY#, andDEVSEL# are allasserted, it indicates that this transfer is the last and at least one data word is transferred. WhenSTOP# and DEVSEL# are asserted and TRDY# is deasserted after previous data transfers, itindicates that the most recent transfer was the last.4.10.2.3 Target-AbortA Target-Abort differs from a Retry or a Disconnect when STOP# is asserted and DEVSEL# hasbeen deasserted.During all transactions crossing the bridge, except posted writes, the bridge will signal aTarget-Abort to the initiator on the initiating bus when a Target-Abort is received by the bridge onthe target bus. The bridge will set the Target Abort (master) bit in the target bus status register (PSRor SSR) and the Target Abort (target) bit in the initiating bus status register. (An exception to thisrule can occur in the case where a target inserts data-to-data wait states after the initial Qword ofdata. When the bridge is forced to disconnect with data on the initiating side, due to the fact that thebridge does not insert data-to-data wait states as a slave, and a target-abort is then signalled by thetarget after the bridge has disconnected with the master, the target-abort will not be reflected backto the master and the Target Abort (target) bit in the initiating bus status register will not be set.)When the bridge detects a Target-Abort during a posted write transaction on the target bus and thewrite is still in progress on the initiating bus, the bridge will signal a Target-Abort to the initiator onthe initiating bus. The bridge will set the Target Abort (master) bit in the target bus status register(PSR or SSR) and the Target Abort (target) bit in the initiating bus status register. The error must besignaled on the originating bus in the same data phase in which it occurred on the destination bus.When the posted write transaction is complete on the initiating interface, the bridge will assertP_SERR# (when enabled) on the Primary interface indicating a system error. The bridge will alsoset the Target Abort (master) bit in the target bus status register (PSR or SSR).Developer’s Manual 4-65