Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.23 Extended Bridge Control Register - EBCRThe Extended Bridge Control Register controls the extended functionality the bridge implementsover the base PCI-to-PCI Bridge Architecture Specification, Revision 1.1.Table 4-46. Extended Bridge Control Register - EBCR (Sheet 1 of 2)IOPAttributes15 12 8 4 0rv rv rv rw ro ro ro ro rv rw rw rv rw rw rw rwPCIAttributesrvrvrvrwrororororvrw rwrvrwrorw rwPCI Configuration Offset40 - 41HIntel ® 80200 Processor Local Bus Address0000 1040HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:13 0000 2 Reserved.1211100908Varies withinverse of theexternal stateof RAD[2]/SPMEM# atPrimary PCIbus resetVaries withexternal stateof S_M66ENat SecondaryPCI bus resetVaries withexternal stateof P_M66ENat PrimaryPCI bus resetVaries withexternal stateofS_REQ64#at SecondaryPCI bus resetVaries withexternal stateofP_REQ64#at PrimaryPCI bus reset07 0 2 Reserved.Special Downstream Window Enable - When set, a special downstream memory window whichincludes the addresses FEC0_0000h through FECF_FFFFh is opened.This window provides support for an alternate address mechanism to a Hot-Plug Controller.When clear, the Special Downstream Memory window is closedSecondary Bus Operating at 66 MHz - When set, the Secondary interface has been initialized tofunction at 66 MHz by the assertion of S_M66EN during bus initialization. When clear, the Secondaryinterface has been initialized as a 33 MHz bus.Primary Bus Operating at 66 MHz - When set, the Primary interface has been initialized to function at66 MHz by the assertion of P_M66EN during bus initialization. When clear, the Primary interface hasbeen initialized as a 33 MHz bus.Secondary PCI Bus 64-Bit Capable - When clear, the Secondary PCI bus interface has been configuredas 64-bit capable by the assertion of S_REQ64# on the rising edge of S_RST#. Whenset,theSecondary PCI interface is configured as 32-bit only.Primary PCI Bus 64-Bit Capable - When clear, the Primary PCI bus interface has been configured as64-bit capable by the assertion of P_REQ64# ontherisingedgeofP_RST#.Whenset,thePrimaryPCIinterface is configured as 32-bit only.06 0 2bridge will be claimed by the bridge and forwarded to the Primary PCI interface with medium decodetiming. When clear, all DAC cycles on the Secondary PCI interface will be claimed with subtractiveSecondary DAC Medium Decode Enable - When set, DAC cycles on the Secondary PCI interface of thedecode timing and forwarded to the Primary PCI interface.Developer’s Manual 4-109