Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.30 Secondary I/O Limit Register - SIOLRSecondary I/O Limit Register bits are used when the Secondary PCI interface is enabled for privateaddress decoding. The Secondary I/O Limit Register defines the upper address (inclusive) of adecoded Secondary address range that is used to determine when to not forward I/O transactionsfrom the Secondary to Primary interface of the bridge. The bridge only supports 16-bit addressingwhich is indicated by a value of 0H in the four least significant bits of the register. The upper 4 bitsare programmed with S_AD[15:12] for the top of the address range. S_AD[11:0] of the baseaddress is always FFFH forcing a 4 Kbyte I/O range granularity.For the purposes of address decoding, the bridge assumes that S_AD[31:16], the upper 16 addressbits of the I/O address, are zero. The bridge must still perform the address decode on the full 32 bitsof address per PCI Local Bus Specification and check that the upper 16 bits are equal to 0000H.Table 4-51.Secondary I/O Limit Register - SIOLRIOPAttributes7 4 0rw rw rw rw ro ro ro roPCIAttributesrw rw rw rwrorororoPCI Configuration Offset55HIntel ® 80200 Processor Local Bus Address0000 1055HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:04 0H03:00 0HSecondary I/O Limit Address - This field is programmed with S_AD[15:12] of the top of the private I/Oaddress range not passed from the Secondary to Primary interface.Secondary I/O Addressing Capability - The value of 0H signifies that the bridge only supports 16-bit I/Oaddressing.Developer’s Manual 4-117