Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.3.5 SDRAM InitializationFigure 3-9.Since SDRAM devices contain a controller within the device, the MCU must initialize themspecifically. Upon the deassertion of I_RST#, software initializes the SDRAM devices with thesequence illustrated with Figure 3-10:1. The MCU applies the clock (DCLKOUT[3:0]) at power up along with system power (clockfrequency unknown).2. The MCU must stabilize DCLKOUT[3:0] within 100 µs after power stabilizes.3. The MCU holds all the control inputs inactive (SRAS#, SCAS#, SWE#, SCE[1:0]# = 1) anddeasserts SCKE[1:0] for a minimum of 1 ms after supply voltage reaches the desired level.Asserting P_RST# achieves this state.4. Software disables the refresh counter by setting the RFR to zero.5. Software issues one NOP cycle after the 1 ms device deselect. A NOP is accomplished bysetting the SDIR to 011 2 .TheMCUassertsSCKE[1:0] with the NOP.6. Software pauses 200 µsec after the NOP.7. Software re-enables the refresh counter by setting the RFR to the required value.8. Software issues a precharge-all command to the SDRAM interface by setting the SDIR to010 2 .9. Software provides eight auto-refresh cycles. An auto-refresh cycle is accomplished bysetting the SDIR to 100 2 . Software must ensure at least T rc cycles between each auto-refreshcommand.10. Software issues a mode-register-select commandbywritingtotheSDIRtoprogramtheSDRAM parameters. Setting the SDIR to 000 2 programs the MCU for CAS Latency of twowhile setting the SDIR to 001 2 programs the MCU for CAS Latency of three. The MCUsupports the following SDRAM mode parameters:a. CAS Latency (CL) = three or twob. Wrap Type (WT) = Sequentialc. Burst Length (BL) = fourSupported SDRAM Mode Register SettingsA1100 00 0A0Burst Length:010: 4Other: XBurst Type:0: Sequential1: X (Interleaved)CAS Latency:010: 2011: 3Other: XThe SDRAM mode register residesin the SDRAM devices.11. The MCU may issue a row-activate command three clocks after the mode-register-setcommand (T mrd ).Developer’s Manual 3-19