Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.40 PMCSR PCI-to-PCI Bridge Support - PMCSR_BSEThis register supports Bridge specific Power Management Control/Status functionality and isrequired for all PCI-to-PCI bridges.Table 4-61.PMCSR PCI-to-PCI Bridge Support - PMCSR_BSEIOPAttributes7 4 0rw rw ro ro ro ro ro roPCIAttributesrorororororororoPCI Configuration Offset6EHIntel ® 80200 Processor Local Bus Address0000 106EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07 0 2BPCC_En (Bus Power/Clock Control Enable) - When this bit is set the Power State field in the PMCSRregister can be used to control the Secondary bus Power/Clock.06 0 2B2_B3# (B2/B3 support for D3 hot ) - When BPCC_EN (bit 07) is set, the state of this bit determines theaction that is to occur as a direct result of programming the Power State field of the PMCSR from D0 toD3 hot .When this bit is set, the Secondary bus PCI clock will be stopped (B2) when the Power State field of thePMCSR is programmed to D3 hot and BPCC_EN is set.When this bit is cleared, the Secondary bus will have its power removed (B3) when the Power State fieldofthePMCSRisprogrammedtoD3 hot and BPCC_EN is set.5:0 000000 2 Reserved.4-128 Developer’s Manual
PCI Address Translation Unit 5This chapter describes the operation modes, setup, and implementation of the mechanism whichinterfaces between the primary and secondary PCI busses and the Intel ® 80312 I/O companionchip internal bus.5.1 OverviewAs indicated in Figure 5-1, the ATU — the interface between the PCI bus and the on-chip internalbus — consists of two address translation units, the Expansion ROM Unit and the Messaging Unit(MU) described in Chapter 6, “Messaging Unit”The ATUs support both inbound and outbound address translation. The ATUs are:• Primary ATU (PATU) — provides access between the primary PCI bus and the Intel ® 80312I/O companion chip internal bus. The primary ATU and Messaging Unit share PCI addressspace.• Secondary ATU (SATU) — provides access between the secondary PCI bus and the Intel ®80312 I/O companion chip internal bus.Transactions initiated on a PCI bus and targeted at the Intel ® 80312 I/O companion chip internalbus are referred to as inbound transactions (PCI to internal bus); transactions initiated on the Intel ®80312 I/O companion chip internal bus and targeted at a PCI bus are referred to as outboundtransactions (internal bus to PCI). The ATU handles multiple inbound PCI transactions; it cansimultaneously process PCI read and write transactions.During inbound transactions, the ATU converts PCI addresses (initiated by a PCI bus master) tolocal bus addresses and initiates the data transfer on the Intel ® 80312 I/O companion chip internalbus. During outbound transactions, the ATU converts local bus addresses to PCI addresses andinitiates the data transfer on the respective PCI bus.The Messaging Unit provides a mechanism for the system processor and the Intel ® 80312 I/Ocompanion chip to transfer control information. The Messaging Unit occupies the first 4 Kbytes ofthe Primary ATU address space. PCI masters on the primary interface of the Intel ® 80312 I/Ocompanion chip access the MU by addressing the PATU anywhere in the first 4 KB offset from thePATU Base Address Register. When the Secondary Bus Messaging Unit Access mode is enabled,secondary PCI masters can access the MU by forwarding transactions through the PCI-to-PCIBridge Unit.The Expansion ROM provides the PCI mechanism for downloading device/board driver codeduring system boot sequence. It consists of a separate inbound address range which accesses aFlash EPROM device connected through the Intel ® 80312 I/O companion chip memory controller.Refer to the PCI Local Bus Specification, Revision 2.2 for details of Expansion ROM usage.The Primary and Secondary Address Translation Units, the Expansion ROM Translation Unit, andthe Messaging Unit appear as a single PCI device on the primary PCI bus. These units collectivelyare the second PCI function in the multi-function Intel ® 80312 I/O companion chip. (Refer toSection 5.2.4 for exceptions to this statement.) The block diagram for the ATUs and the MessagingUnit is shown in Figure 5-1.Developer’s Manual 5-1
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Intel 80312 I/O Companion Chip - ECEE

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