Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMessaging Unit6.2 Theory of OperationThe MU has four independent messaging mechanisms. The four Message Registers are similar to acombination of mailbox and doorbell registers. Each holds a 32-bit value and generates an interruptwhen written.The two Doorbell Registers support software interrupts. When a bit is set in a Doorbell Register, aninterrupt is generated.The Circular Queues support a message passing scheme that uses four circular queues. The fourcircular queues are implemented in the Intel ® 80200 processor local memory. Two queues are usedfor inbound messages and two are used for outbound messages. Interrupts may be generated whenthe queue is written.The Index Registers use a portion of the Intel ® 80200 processor local memory to implement a largeset of message registers. When one of the Index Registers is written, an interrupt is generated andthe address of the register written is captured.Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and theOutbound Interrupt Status Register. Each interrupt generated by the Messaging Unit can be masked.Multi-word PCI burst accesses are not supported by the Messaging Unit, with the exception ofmulti-word reads to the index registers. The MU terminates multi-word PCI transactions (otherthan index register reads) with a disconnect after the next Qword boundary, with the exception ofqueue ports.All registers needed to configure and control the Messaging Unit are memory-mapped registers.The MU uses the first 4 Kbytes of the primary inbound translation window in the Primary AddressTranslation Unit (PATU). This PCI address window is used for PCI transactions that access theIntel ® 80200 processor local memory. The PCI address of the primary inbound translation windowis contained in the Primary Inbound ATU Base Address Register. See Chapter5,“PCIAddressTranslation Unit” for more details on inbound ATU addressing and the PATU.From the PCI perspective, the Messaging Unit is part of the Primary Address Translation Unit. TheMessaging Unit uses the PCI configuration registers of the Primary ATU for control and statusinformation. The Messaging Unit must observe all PCI control bits in the Primary ATU CommandRegister and ATU Configuration Register. The Messaging Unit reports all PCI errors in the PrimaryATU Status Register. The Messaging Unit can be accessed from the Intel ® 80312 I/O companion chipsecondary PCI bus by sending the cycle through the PCI-to-PCI Bridge Unit. Refer to Chapter 4,“PCI-to-PCI Bridge Unit” for details of the correct configuration options to support this feature.Parts of the Messaging Unit can be accessed as a 64-bit PCI device. The register interface, messageregisters, doorbell registers, and index registers return a P_ACK64# in response to a P_REQ64# onthe primary interface. Up to 1 Qword of data can be read or written per transaction (except IndexRegister reads, see Section6.6,onpage6-15). The Inbound and Outbound Queue Ports are always32-bit addresses and the MU never asserts P_ACK64# to offsets 40H and 44H.6-2 Developer’s Manual
Intel ® 80312 I/O Companion ChipMessaging UnitFigure 6-1.PCI Memory MapFirst 4 Kbytes of thePrimary ATU Inbound PCI Address Space0000H0004H0008H000CH0010H0014H0018H001CH0020H0024H0028H002CH0030H0034H0038H003CH0040H0044H0048H004CH0050HReservedReservedReservedReservedInbound Message Register 0Inbound Message Register 1Outbound Message Register 0Outbound Message Register 1Inbound Doorbell RegisterInbound Interrupt Status RegisterInbound Interrupt Mask RegisterOutbound Doorbell RegisterOutbound Interrupt Status RegisterOutbound Interrupt Mask RegisterReservedReservedInbound Queue PortOutbound Queue PortReservedReserved4 Message Registers2 Doorbell Registersand4 Interrupt Registers2 Queue PortsIntel ® 80312 I/OCompanion ChipLocal Memory1004 Index Registers0FFCHA8264-01Table 6-1 provides a summary of the four messaging mechanisms used in the Messaging Unit.Table 6-1.MU SummaryMechanismQuantityAssert PCI InterruptSignals?Generate Intel ® 80200Processor Interrupt?Message Registers 2 Inbound and 2 Outbound Optional OptionalDoorbell Registers 1 Inbound and 1 Outbound Optional OptionalCircular Queues 4 Circular Queues Under certain conditions Under certain conditionsIndex Registers 1004 32-bit Memory Locations No OptionalDeveloper’s Manual 6-3
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Intel 80312 I/O Companion Chip - ECEE

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